Headband outline, placement and routing

First placement: 2026-10-25. Source: espurr-band.kicad_pcb. The design reference owns interfaces and selections; the rigid-board rules own the selected nominal 1.6mm, four-layer JLC04161H-7628 stack and USB geometry.

Current state: the 2026-11-07 manual routing and label review below supersedes the 2 November silk release. Older records remain history.

Manual routing and label review — 2026-11-07

Andi's saved edits move R130 from (109.95,110.95)mm to (109.95,108.95)mm and the front logo from (111.0,119.05)mm to (111.5,118.25)mm, with further label/pointer adjustments. PDM, I2C1, right-ear LED, CC interrupt and local 3.3V routes are reworked; several stitching/transition vias move and redundant HUSB ground segments are removed. There are 755 copper track/via objects, down from 759.

Native comparison confirms unchanged pad nets, board outline, zone outlines, all other footprint poses, right-board copper, USB D+/D− and the local buck copper. The 5V tracks are identical; refilled supply pours have no lost copper beyond the existing 11µm CAM tolerance. USB remains 0.2032mm / 8mil with L2/L3 ground coverage outside the intentional transition antipads. Saved/refilled DRC, schematic parity and ERC are checked on disposable copies; the repository's 143 tests pass. No source routing correction was needed during this review. BOM content is unchanged, and R130 is the only fitted placement change.

Evidence and the new delivery are under build/headband-manual-release-20261107/; review/routing-audit.json contains the geometry checks and per-net route lengths. The earlier source is snapshotted alongside the exact user save. Software/CAM checks do not establish physical current, thermal, RF or sensing performance.

Chip labels, branding and QR — 2026-11-02

All nine U references are on B.Silkscreen beside projected package-body outlines, using the native F.Fab body geometry and its pin-1 chamfers. These replace the intermediate boxes around the reference text. References use 0.8mm height and 0.15mm strokes; the eight small ICs have adjacent references, while U101 remains inside its module outline, between TX/RX and BOOT at (124, 134.1)mm. The module projection stops at the PCB boundary; its three on-board sides are continuous after moving the artwork clear. Front labels are ESP32, USB CC, Buck, IMU, ALS, INA and LDO. Seven short leaders identify the less obvious associations, with axis-aligned stems, R0.25mm bends where needed, and conventional arrowheads. Passive references remain hidden. The UART text and rear board-name text move to clear the new artwork; the actual test pads and all component positions stay fixed.

The rear board names are espurr v2 band L and espurr v2 band R. The left board name uses explicit centre/centre alignment at (125.275, 116.875)mm: the centre of the strip spanning x115.55–135mm between the 115mm board edge and the 118.75mm module-outline edge. The previous title was centred vertically but kept the old x119mm anchor, outside the centre of that strip. All twelve visible right-main silk labels, on both faces, are rotated 180° about their existing anchors; keep-upright is disabled for them. Footprints, package body projections and connector polarity locations do not move. The later connector-label polish keeps that reversed right-board reading direction, except Mic R, now at 90° along its socket's long edge at (108.65, 80.8)mm. Connector names are Ear L/R, Mic L/R and Band. The Band labels move closer to their sockets, to y106.3mm on the left and y85.55mm on the right; their short orthogonal leaders use R0.25mm bends. Both microphone labels have short pointers. Both microphone labels now use 0.8mm text along their sockets' long edges: Mic L is at (108.3, 111.2)mm, rotated 90° counterclockwise to the left of J103; Mic R is at 90° beside J203 after the requested 180° text-only flip; its position and pointer stay fixed. Both have short horizontal pointers. Other connector lettering remains 1mm. The left INA label moves to (101.6, 118.65)mm, left of U106, with a short straight pointer replacing the former loop around the chip. The bridge's six signal labels and four power legends use 0.8mm text with 0.15mm strokes. The A/B arrows retain their manual straight paths but now match the device leaders' 0.15mm stroke and 0.3 × 0.36mm arrowheads. The neggles.dev logo from neggles/esp-pmsa is below the left board name, shifted left in the rear view to (121, 122.2)mm, with its caption directly below at (121, 126.2)mm. Both now clear the continuous module outline. The filled derivative preserves the central diamond opening and the outer bounds of the original 45 Bezier curves and 0.127mm strokes, approximately 7.545 × 5.516mm. The original outline library asset is retained. The logo and QR footprints live in the shared project library and are PCB-only, pad-free, excluded from BOM and placement exports. See asset provenance.

QR101 is a solid 5 × 5mm B.Silkscreen replacement target, authorised after an 8mm target could not clear all drills. Its bounds are x127.75–132.75 / y119.75–124.75mm after moving 0.5mm left and 0.75mm down in the rear view. The whole 25mm² sits over the rear GND_L pour, with no rear traces underneath and 0.61mm minimum clearance to a drill edge. No solder-mask opening or copper change is added. Use the JLC marking settings and inspect the supplier-processed rear barcode layer before approval.

The rear USB legend is two lines, USB-C and 5V 3A, centred at (112, 142.5)mm. J101's 16 numbered contacts are top copper/mask/paste only; the four shell anchors are intentionally plated through. The apparent rear contact comb was the 3D model: its contact seating face is at Z=-1.68mm. A +1.68mm model offset, applied to the board and shared footprint, seats it correctly. Hiding the model independently removed the apparent contacts; no pad, mask, copper or connector pose was changed.

Evidence: build/headband-mic-r-text-20261102/. The saved project now uses the authorised 0.8mm minimum silkscreen text height, retaining 0.15mm minimum text strokes. Native project save/readback confirms this is the only project settings change. Source DRC has zero violations, opens or schematic-parity findings. JLC's silkscreen guide lists a 0.8mm lower limit (checked 2026-11-02); supplier artwork preview remains part of ordering. Native readback verifies all existing pads/nets, poses, tracks/vias, outline and zone definitions/fills unchanged. Latest panel: build/headband-mic-r-text-20261102/release/build/panel/; matching renders and the review page are under build/headband-mic-r-text-20261102/. The release directory freezes the committed runner and design inputs to isolate generation from concurrent mic-flex and website work.

Silkscreen and download names — 2026-11-01

Both saved silkscreen layers now specify White, retaining green solder mask and the existing JLC7628 stack geometry. Front labels identify EAR L/R, MIC L/R, BAND and the power-connector +/− contacts. Polarity is checked against pad nets: J105.2 and J205.1 are +5V; J105.1 and J205.2 are ground. The temporary bridge is labelled SCL/SDA/CLK/DAT/OUT/IN at JP101–JP106, with +/− and 5V/0V at JP108/JP109. These are right-side link functions. Board names and a SNAP OFF legend are on the rear. Only U references remain visible alongside the functional labels; R132, R202 and L101 were hidden in the follow-up simplification. The right INA232 reference is on the rear directly beneath the component.

All added text uses at least 1mm height and 0.15mm strokes. Source DRC/parity has zero findings. Independent native readback proves that component poses, numbered pads/nets, tracks/vias, outlines, zone definitions and fills are unchanged. Initial evidence: build/headband-silk-20261101/; hash/label follow-up: build/headband-design-revision-20261101/. Production packages now carry board name plus an eight-character design-input hash, with separate unit/panel prefixes and a combined download ZIP; see the quote guide. Latest panel: build/headband-wroom-panel-20261101-design-hash/; matching renders: build/renders/headband-20261101-final-silk/. The regenerated unit has zero ERC/DRC/parity findings. The two-set panel passes pad/net/pose, copper-CAM, drill and printed-text transformation checks, with only the four existing U101/MB101 library differences. The follow-up hash/label revision passes all 132 tooling tests. Two independent fresh unit exports produced the same design revision despite different timestamped Gerber ZIPs; BOM/CPL bytes also match. The evidence is in build/headband-design-revision-20261101/rebuild-stability.json. Supplier placement preview and physical acceptance remain open.

Manual-routing review — 2026-11-01

8660ff5 checkpoints Andi's manual routing and passive-placement changes before correction. Nine left-side passives moved; the board outline, 24-hole bridge, 8.5mm R0.5 slot, connector/module poses and numbered-pad net assignments stayed unchanged. BX audio data shortens from 50.16mm to 23.58mm and BCLK from 47.06mm to 27.47mm. The project diff changes zone drawing defaults only; existing zone clearance/connection settings and DRC thresholds are unchanged.

The focused review found one ground-via/CC_INT_N spacing violation, a 0.5mm leftover I2C1_SCL stub, two ground stitches narrowing the rear 5V spine to 1.4225mm, a PDM-clock via clipping that spine, and L2 CC/audio routes crossing below the front USB pair. ERC, numbered-pad parity and connectivity were already clear.

Corrections preserve every manual component position, electrical pad, outline and zone definition. Four vias move: the CC interrupt neighbour to (113.275,129.3), the two supply-intruding ground stitches to x=112.55 at their original y=130.95 / 132.775, and PDM_CLK_R from (111.4,111.7) to (111.5,111.7). A short 45° exit keeps the PDM clocks' spacing; the dangling SCL stub is removed. CC2, CC_INT_N and the three BX audio nets retain their XY routing but move their L2 segments to L3, restoring the USB ground reference. All other manually saved copper is retained.

Refilled DRC, ERC, connectivity and schematic parity pass with zero findings. Saved readback verifies the precise correction boundary and unchanged net identities. Both USB routed faces have continuous projected ground reference away from their via transitions. The 5V spine is again 2mm wide; the manual USB crossfeed remains 1.475mm. Both post-shunt feeds remain 1.3mm, and the main 3.3V and right-side supply plane-path checks pass. The buck switching/feedback routes and all right-side routing are retained. These are CAD routing checks, not a new thermal, RF or mounted-hardware qualification. All 130 tooling tests pass.

Evidence and original saved snapshot: build/headband-manual-review-20261101/. The refreshed package is build/headband-wroom-panel-20261101-rerouted/, with matching separate board/panel views under build/renders/headband-20261101-rerouted/.

Bridge perforations and USB model — 2026-11-01

The L/R electrical-test bridge now has 24 NPTH holes, up from 18, in two straight rows at y=92/100mm. The six power-side interior holes increase from 0.5mm to 0.7mm diameter. New 0.5mm holes are centred on the outside borders and both sides of the slot. At the left outside edge, the border hole replaces its adjacent interior hole to retain drill clearance without moving traces. There are no staggered holes. The internal slot is 2 × 8.5mm with four 0.5mm-radius corners. Its flat ends at y=91.75/100.25mm align with the outer edges of the adjacent 0.5mm drills, replacing the earlier 9.2mm slot. The slot-adjacent holes intersect the rounded corners; their positions remain unchanged.

All traces/vias, electrical pads, component poses, jumper positions, zone outlines and the outer board outline are unchanged. The power test tracks retain their 0.75mm width and have 0.275mm clearance to the larger holes. The minimum hole-edge spacing is 0.3mm. Refill, full DRC, connectivity and schematic parity pass with no findings. Local filled copper retreats around the larger holes and slot where required; no supply route is moved or narrowed by hand.

The source J101 and GT-USB-7010AO_BandOverhang shared footprint retain only the existing ${KICAD_USER_3DMODEL_DIR}/C963413.step model. The unresolved alternative USB_C_Receptacle_G-Switch_GT-USB-7010ASV.step is removed; pad geometry and the retained model transform are unchanged.

Evidence: build/headband-bridge-20261101/ contains the pre-edit snapshot, source promotion hashes, before/after native geometry, DRC and a visual comparison. The pre-change slot is a true capsule in both native geometry and the unit/panel Edge.Cuts Gerbers (two straight sides, two 1mm-radius semicircles); no extra semicircular cut was found in manufacturing geometry. At the slot-alignment checkpoint, build/headband-wroom-panel-20261101-aligned/ and its raytraced views still contained the preceding 9.2mm slot. They remain historical inputs. build/headband-slot-alignment-20261101/ retains the 8.5mm revision snapshot, native readback, clean DRC, promotion hashes and preview. The later manual-routing package described above includes that alignment.

Supply-pour audit — 2026-10-31

Move the left-ear SDA transition from (105.2,113.65) to (104.55,111.75), behind its signal contact and out of the R132-to-J102 power strip. The broader audit also finds CC1/CC2 transition clearances cutting the USB entry/crossfeed, beyond the previous y=106–136mm spine check. Move those vias to (108.5,136.25) and (113.75,136) respectively. Only the three vias and their local SDA/CC routes change; all components, pad geometry, buck copper, USB data routing, other copper, outlines and zone definitions are held.

Checked supply corridor	Before	After
Left ear after R132	0.6225mm	1.3000mm
Right ear after R202	1.3000mm	1.3000mm
Shared rear spine, including USB entry	1.2450mm	≈2.0000mm
USB rear crossfeed	0.9725mm	1.5000mm
Left shunt and buck input landings	0.9000mm	0.9000mm
Each USB contact entry	0.7450mm	0.7450mm
Right inner vertical arm	3.4925mm	3.4925mm
Right inner horizontal arm	2.6755mm	2.6755mm

Widths come from 0.01mm cross-section sampling between the relevant terminals; rounded dead ends beyond terminals are excluded. The 1.99904mm endpoint result is approximately 2mm within the polygon/tessellation tolerance. The 0.745mm USB entries are existing adjacent-contact clearance constrictions, not via cutouts. All small 5V pour outlines are clear of foreign-via clearance intrusions. The right inner distribution retains its original foreign-via holes with the broad remaining arms recorded above.

Filled-plane erosion checks retain a 1.0mm geometric route between the left buck-output and MCU plane landings, a 0.5mm route across the right 3.3V plane, and a 1.5mm route through the right 5V distribution. These use a 0.35mm terminal approach allowance and do not establish trace/via ampacity or thermal behaviour. The existing low-current branches connecting separate 3.3V regions are retained. USB L2/L3 reference coverage, all 78 component poses and every non-edited copper item are independently checked. Refilled DRC has zero violations, opens and schematic-parity findings; the schematics are unchanged.

Evidence and before/after views: build/headband-supply-audit-20261031/. The earlier statement that the full spine had been checked was too broad: its sampling stopped before the USB-entry cutouts. This audit covers those as well.

Full-width 5V restoration — 2026-10-31

The BX word-clock via moves from (111,133.5) to (108.5,134), outside the left edge of the rear 5V spine. Its three nearby segments are adjusted and one short 45-degree L3 segment is added. The width check also identified a second identical neck caused by the ground stitch at (111,128.5), which now sits at (113.7,128.7) in the existing USB ground-reference patch. The previous summary attributed the neck only to the signal via; both clearances contributed.

Native filled-copper inspection restores the minimum sampled total corridor width from 1.5225mm to 2.0000mm, checked every 0.01mm over y=106–136mm. The rear 5V copper remains one connected region. USB reference coverage remains complete over the checked front/L2 and rear/L3 projections, with the existing 0.7mm transition-antipad exclusions.

All 78 component poses and pad geometry, the outline, zone definitions, buck copper, USB data routing and every other track/via are unchanged. No schematic or pin-map change is made. Independent saved checks and refilled DRC find zero violations, opens or parity findings. Evidence and before/after copper views are in build/headband-5v-width-20261031/; manufacturing files are not regenerated.

Manual-layout routing completion — 2026-10-31

Andi's saved manual layout, schematic and shared-footprint/model changes are checkpointed unchanged in 8c6fdc7. This supersedes the earlier placement and routing acceptance: the right board is rebuilt, the joined outline is now 35 × 73.5mm, and the left placement/USB routing are manually revised. The local Pico-EZmate library copy adds a 3D model to the bundled land pattern; it is not a new connector geometry.

Routing completion holds all 78 footprint poses, including 20 locked footprints, every pad's copper geometry, the outline and all zone definitions. The right-board tracks/vias, manual buck copper and all 42 USB tracks/vias are preserved. The only removed original copper is two duplicate bridge segments, an obsolete 3.3V tail/via, and four HUSB strap segments replaced to make room for its VBUS-detect escape. No autorouter was used.

The remaining I2C, LED/PDM, HUSB, BX audio and reset connections are completed. Nine newly added right-angle corners are chamfered. Local ground pad overrides resolve starved thermals, and stitches connect the isolated ALS/reset ground regions. Two low-current 3.3V branches reconnect regions separated by signal clearances. The broad rear 5V region remains connected; its minimum sampled total corridor width is 1.5225mm, compared with 2.0mm in the manual input, because of the added signal-via clearance. This is a local neck, not a new qualification of the shared supply's current/drop/thermal behaviour.

Andi approved swapping the right LED assignments to follow the connector order: GPIO6 / pad 6 → right outer through R116; GPIO7 / pad 7 → right inner through R115. Left LED assignments and connector pinouts are unchanged. The schematic labels/annotation and current GPIO table reflect the swap. The firmware handoff records the outstanding firmware change; firmware remains read-only here.

Independent saved checks compare every original track/via and pad net, rather than relying solely on DRC. This caught and corrected an unintended live-editor net reassignment of a buck ground stitch. The module's exact manual geometry was also restored after an IPC whole-footprint round-trip caused a library mismatch. All remaining original copper matches the checkpoint exactly, apart from the eight explicitly approved LED net-name swaps. Native filled-copper checks find no gaps beneath the USB trace projection over L2/L3, excluding 0.7mm around its four existing transition antipads. The user's 0.2032mm USB traces are unchanged; the earlier calculator geometry is not silently reapplied.

Evidence is in build/headband-manual-finish-20261031/: source snapshot and hashes, explicit manual routing scripts, saved geometry, four-layer review, exported netlist, ERC, refilled DRC/parity and preservation checks. Final software checks have zero DRC violations, opens and parity findings, with clean band ERC. Visual acceptance, updated manufacturing outputs and mounted electrical/RF/fit qualification remain separate gates.

Routing sanity cleanup — 2026-10-31

U105's I2C0 SCL route now stays on B.Cu until the final via at (112.25,133.75). The redundant via at (112.25,132.5) and short L2 hop are removed. R132's two 0.6/0.3mm 5V feed vias are aligned with its input land at (108.375,115.75) and (109,115.75). The nearer drill is 0.125mm clear of the land edge; the independent Kelvin sense route is unchanged. A wider spacing trial conflicted with the existing L3 LED route and was rejected.

Local supply widths follow their loads: 0.15mm pull-up branches, 0.20–0.25mm sensor/microphone bypass links, and 0.30mm right-LDO output connections. The 0.50mm MCU supply feed is retained. The short upstream ALS supply section remains 0.15mm to clear BOOT, with a wider local capacitor connection. Small tilted escapes and unnecessary jogs around both sensor sections, pull-ups and service signals are replaced with straight/45-degree segments. All non-buck track segments now follow horizontal, vertical or 45-degree axes; this does not prohibit pad junctions or alter the preserved buck geometry.

Every footprint pose, all pad/net assignments, the outline, zone definitions and project rules are unchanged. All 40 buck tracks/vias and 32 USB tracks/vias match the pre-cleanup snapshot exactly. Filled-copper checks retain the USB reference coverage, 0.6366mm rear pour setback, continuous rear 5V region and 2.145mm minimum sampled total corridor width. No loss of L2 ground is found in the local buck-return comparison region.

Edits used an isolated owned native IPC editor, with saved native readback and four-layer visual review. Evidence is in build/headband-routing-sanity-20261031/: snapshot, explicit edit plan, IPC receipts, saved geometry, layer review and independent validation. Refilled DRC reports zero violations, opens and schematic-parity findings; band ERC is clean. No autorouter was used. Manufacturing outputs have not been refreshed; mounted current, USB and RF qualification remain separate gates.

USB socket resistors and rear pair — 2026-10-31

R101/R102 now sit immediately above the USB-C pads at (111.25,136) and (112.75,136), both −90°. C123 moves to (114.25,136.25), 180°, to clear the local escape. All other component poses, all 15 locked placements, the outline and all 40 buck tracks/vias are unchanged from 74a5d3b.

The socket joins and resistor connections stay on F.Cu. Each MCU-side USB net then uses one via onto B.Cu and one back onto F.Cu directly beneath its WROOM pad. The main rear run is coupled at 0.218694mm width / approximately 0.1313mm edge gap. The symmetric 7628 outer-layer stack retains the adopted 90Ω non-coplanar geometry on either face; this is not a measured impedance claim. The front sections reference L2; the rear section references L3.

Two simple, higher-priority L3 GND regions override the 3.3V pour beneath the rear pair. A B.Cu pour keepout maintains at least 0.6366mm same-layer pour setback on the checked route portions. Ground stitching joins L2/L3 near the transitions. BX clocks/data, IRQs, CC interrupt and local I2C/BOOT crossings move to L2 where needed to avoid cutting the USB reference. The left CC interrupt leg stays on L3; native filled-copper comparison finds no lost L2 ground within the buck return region (x=103–111.2, y=122.75–131mm). The ALS supply bypass is connected locally on F.Cu. The rear 5V region remains continuous and retains its 2.145mm minimum sampled total width; no current qualification is inferred.

Saved evidence in build/headband-usb-rear-20261031/ includes the four-layer review, pre-edit snapshot, explicit native edit script and independent checks. DRC has zero errors, warnings, opens or parity findings; ERC is clean. Native filled-polygon checks find no gaps beneath the projected USB copper, excluding 0.7mm around the four intentional transition antipads. Both conductors have two through vias. MCU-side copper lengths, excluding via barrels, are about 20.648mm D− / 18.906mm D+; local pad/via fanout is not continuously coupled and no serpentine tuning is added. Locked poses, buck copper and all pad-net assignments are independently compared with the saved baseline.

The layout is ready for visual review. Exact module sourcing/CPL rotation, regenerated WROOM panel/manufacturing outputs and physical USB/current/RF qualification remain separate gates.

WROOM manual routing checkpoint — 2026-10-31

The 35 × 72mm joined outline, all 15 locked footprint poses, eight buck component poses and all 40 tracks/vias translated with the buck are unchanged. No autorouter or path search was used. New right-angle corners were chamfered into 45-degree segments; the held buck and USB geometry was not rewritten by that cleanup.

The rear 5V_L spine is a single continuous filled region. Small front zones serve the socket, shunt and cross-band power connector. Signal crossings, including the mic-select strap, no longer sever the rear feed. L3 has a simple priority-based 3.3V distribution region; smaller power zones override defaults. The narrow left-side front 3.3V region and a short rear HUSB bypass connection join the low-current local supply islands. The buck LX copper is held.

The left ALS U105 moves to (113.75,133.5), 180°, with C123 at (113.5,136), 90°. BOOT pull-up R104 is at (113.75,129.5), 90°. JP1 is at (118.75,134.25), B.Cu; UART probe pads remain at their approved positions. Pull-ups, clock/source resistors and HUSB straps are arranged around the fixed module and connectors. No GPIO, I2C address, connector mapping or component value changes are made. C116 was already removed in c925ec1.

U101 now uses the WROOM-1-only underside ground and paste geometry. The extra overlapping WROOM-2 ground rectangle is removed. Project-global footprint variants trim only off-board/colliding silkscreen for U101, J101 and U203; numbered copper, drill and paste geometry remain unchanged from their selected base patterns. See the library record.

Saved native evidence in build/headband-wroom-routing-20261031/ includes an interactive four-layer review, net-coloured native geometry, source hashes and held-geometry checks. Refilling with KiCad 10 and running full-track DRC gives zero errors, zero warnings, zero opens and zero schematic-parity findings. Standalone ERC is clean; exported schematic pin/net membership is unchanged. The rear 5V region has at least 2.145mm total copper width on sampled transverse sections through the 3mm-wide main corridor (0.1mm sample interval). This is geometric evidence, not a via/connector/cable/thermal current qualification.

Subsequently completed above: move R101/R102 immediately above the socket pads and route part of the pair on B.Cu, with a continuous L3 ground reference under that section. This checkpoint retains the front pair at 0.218694mm width, about 0.1313mm trunk gap, over L2 ground. The USB revision must preserve the buck and locked poses and repeat DRC/return-plane checks. Existing MINI manufacturing packages are historical; regenerate the WROOM panel/BOM/CPL after layout approval and exact module sourcing/rotation review.

WROOM placement checkpoint — 2026-10-30

This historical placement checkpoint targets ESP32-S3-WROOM-1-N16R8, with 16MB flash and 8MB octal PSRAM. The left main is 35 × 45mm; the joined blank is 35 × 72mm. The right main, bridge outline and connector positions are held. No programming header is fitted. Recovery branch codex/headband-pre-wroom-apply-20261030 retains the pre-edit state at b817aeb; build/headband-wroom-apply-20261030/snapshot/ contains the matching saved source and a hash manifest.

Coordinates are absolute PCB millimetres, component-side view:

Item	Saved placement	Change
WROOM U101	(128.75,127.75), 270°	Antenna rearward; body ends x=141.5, 6.5mm beyond board
USB J101	(112,142.4), 0°	2.5mm forward; cable down
Buck U103	(107,124), 90°	Whole eight-component block and 40 local tracks/vias translated 2mm left
HUSB U102	(102.5,133.5), 90°	Far-left pocket with bypass and strap resistors
RESET / A / B	x=120 / 126 / 132, y=141.5, 90°	Compact row; RC parts between buttons
BOOT JP1	(126.75,138.5), B.Cu	Rear face, not lower PCB edge
UART TX / RX TP103/104	(120.75,138.5) / (122.75,138.5), B.Cu	Rear probe pads; no header
Left ALS U105	(111.5,117), 180°	Shifted left to clear WROOM/USB escape; C123 beside it

TP105/TP106 are removed. The BX, INA232/shunt and FFC/power connectors retain their saved poses. I2C1 pull-ups move beside the new left-edge bus pads; other small passives are rearranged to resolve actual courtyard conflicts. The GPIO table records CC_INT_N=GPIO12, BX BCLK/WCLK=GPIO13/14, and unused pads 24/25/28/29/30. The common ground land has WROOM-1 paste only; see the library record.

Affected lower-left/MCU/USB routing is removed. The five old 5V_L trunk zones are removed for reconstruction around the new USB-to-buck corridor. The buck's local LX zone moves with the block. Left GND zone boundaries narrow to the new edge; the existing 3V3_L L3 region is retained for the upcoming routing pass. Right/bridge routing is retained. No autorouter was used.

Saved native readback verifies the 35mm outline, requested poses/sides, unchanged poses outside this scope, and all schematic pad nets. Standalone and parent ERC have zero findings. Placement DRC has no error-severity geometry/copper/courtyard violations and no schematic-parity findings; 91 opens remain, along with dangling-route/via and silkscreen warnings. These are incomplete-routing evidence, not a fabrication pass. Native preview and detailed checks are under build/headband-wroom-apply-20261030/.

At that checkpoint, next work was to rebuild power trunks, USB pair/fanout and lower-left signals; review the filled planes, finish silkscreen and rerun full DRC/netlist/ERC checks. Select the exact module assembly part and regenerate the panel/quote from the finished source. Existing MINI packages are not WROOM manufacturing outputs.

Historical MINI placement and routing

Checkpoint b9026b0, the 2026-10-27 compact-regulator and monitor-layout revision, contains 88 footprints including the board-only mousebite fixture / 80 nets, one closed connected outline and one internal slot. The module's original RF rule area is retained; two fixture rule areas reserve the bridge for surface links. There are 842 tracks, 176 through vias, 10 board copper-zone objects and two board FFC component keepouts. The reference-ground zones each cover L2 and L3. The eight pre-bridged PCB solder jumpers are routed. Independent refilled DRC has 0 errors, 0 unconnected items and 0 schematic-parity findings; seven silkscreen warnings remain. The compact-regulator revision supersedes the pending actions and counts in the older checkpoints below.

Status 2026-10-27: broader routing arrangement rejected; reset planned. The counts and DRC results above describe that checkpoint, not the subsequent manual working board. Local placement approval and clean DRC did not establish acceptable routing quality. The reset scope below supersedes the previous preservation policy for inherited signal routes. Final silk and physical/cable/thermal qualification remain. The Astra handover preserves the original critique, crash state and recovery points.

Geometry and placement

Coordinates below are component-side millimetres relative to each main's local top/front-view origin. Left: front is x=0, rear is x=37.5. Right: front is x=0, rear is x=16. Crown is up in the installed views; the right main now has its installed orientation on the joined PCB. In KiCad, left origin is (100,100); right origin is now (100,73). All populated parts are on the outward/front copper side.

• Left main: 37.5 × 45mm broad foot, 16mm upper spine, 2mm outer corners. The 5mm band lies beneath its front edge. No mounting holes are guessed.
• Right main: 16 × 19mm, reduced from the previous 16 × 22mm revision by moving U201/C201/C202 between the fixed ear and mic connectors. The original manual outline was 16 × 28mm; 20 × 30mm described an earlier concept. The band remains beneath its frontmost 5mm; mounted fit remains open.
• Joined blank: 37.5 × 72mm PCB bounds, with the right main above the left. The 16 × 8mm web has two perforated tabs and a 2 × 9.2mm rounded routed slot, extending 0.6mm into each main after Andi's manual shortening. Eighteen 0.5mm NPTH holes define fracture rows at KiCad y=92 and y=100. Eight pre-bridged jumpers occupy the disposable material between those rows. There are no V-scores. See the bridge record below.
• Actual S3 body: 15.4 × 20.5mm, wholly supported solder lands and 5.05mm antenna overhang, reaching x=42.55. The stock S2 Fab body is 0.5mm shorter; the actual S3 envelope and extended RF reservation are on User.Drawings. Keep the antenna and surrounding reservation clear of wiring, steel and housing. See the manufacturer dimensions and land pattern, figures 10-1 and 11-1; the library audit records the retained pad pattern.

Anchor	Ref	Local centre x, y	Orientation / intent
Left S3	U101	32.30, 26.70	270°; antenna rearward
USB-C	J101	14.50, 42.40	Cable down; forward shell edge about 10mm behind front; shell slots stay in-board
App 1 / App 2 / reset	SW102 / SW103 / SW101	29.00 / 35.00 / 23.00, all y=41.375	270°; rearward row
Left cross-band / power	J104 / J105	3.80,2.80 / 13.00,3.60	180°; crownward cable exits
Left ear / mic	J102 / J103	3.80,11.60 / 13.80,11.20	180° / 90°; fixed manual poses, provisional 1→1 ear cable
Left current monitor	U106	3.60,18.80	180°; shunt and direct bypass beside the analogue pins
BX	U104	3.25,40.50	Fixed lower/front hard-mounted band-contact region
Left ALS	U105	12.75,17.00	Keep optical window clear
Buck / CC	U103 / U102	9.00,24.00 / 17.75,32.00	Buck 90° in standard SOT-23-5; compact local block; CC beside USB/MCU
Right cross-band / power	J204 / J205	3.80,16.20 / 13.00,15.40	0°; toward bridge; absolute poses held
Right ear / mic	J202 / J203	3.80,7.40 / 13.80,7.80	0° / 90°; fixed manual poses, provisional 1→1 ear cable
Right current monitor	U203	6.25,2.775	0°; shunt and direct bypass beside the analogue pins
Right LDO / ALS	U201 / U202	9.60,8.80 / 12.75,2.00	LDO 90° between FFCs; ALS pose held

Supporting capacitors, pull resistors, source series resistors and service pads have initial positions. Their final placement depends on short current loops, ground returns and routing. C124/C204 are retained provisions; resolve ALS bulk value/sharing with the nearby rail capacitance during the next refinement. Reference/value fields are hidden for this rough stage; silkscreen is unfinished.

Initial placement checks — historical 2026-10-25

The counts and buck placement in the older records below precede the manual SY8089A1/cable changes. The current power-routing checkpoint at the end of this document supersedes their source-state descriptions.

Native KiCad 10.0.7 saved readback matches all 359 unique numbered pad/net pairs from the exported five-sheet schematic, with the generated SA0/SDO net name escaped to KiCad's native spelling. The initial placement had no schematic parity issues; the later jumper check below records the current manual-edit baseline. The original module rule area and solder lands are retained. D101 is removed, its socket/line USB nets are merged, and C128 joins the buck output bank.

Native DRC reports zero courtyard overlaps, inter-footprint shorts, solder-mask bridges, copper-to-edge violations or malformed outlines. The unrouted board has 289 unconnected items. Four footprint silk segments cross the intended S3/USB overhang edges; final board silkscreen cleanup is deferred.

The 2026-10-25 clearance refinement moves HUSB320's eight short-lead land centres outward by 0.025mm, giving 0.150mm minimum copper clearance. The shared local G-Switch USB footprint trims 0.070mm from only the four coincident GND-pad records' peg-facing ends, giving 0.2626mm copper-to-NPTH clearance. Hole positions/drills, signal contacts, power contacts and shell stakes are held. See the library audit. The global 0.127mm copper and 0.25mm hole-clearance rules are unchanged.

The 2026-10-25 refinement replaced all six former 0805 capacitors with 0603s. The buck output uses C111/C112/C128, three JLC Basic 22µF parts. Their applied 2026-10-26 placement is x=10.10/11.80/13.50, y=30.00, all 270°. The design reference records capacitor bias data and qualification limits. U101's placed model now references the locally retained manufacturer STEP. The missing band project variable KICAD_PROJECT_3D_DIR is now set to ${KIPRJMOD}/../packages3D through native IPC; no stack or routing-rule change accompanies that model-path correction.

Konnect's placement scorer cannot establish containment for this concave outline. It also uses courtyard bounding boxes, reporting 18 false S3 overlap pairs around the module's concave body/RF courtyard and two small rectangular approximations around circular test-point courtyards. These are not waived native DRC findings: KiCad checks the actual contours and reports no courtyard overlaps. The scorer's heuristic capacitor associations do not qualify decoupling.

Before routing, review cable exits and clearance over the adjacent crownward FFC sockets, plug/boot envelope around USB, clamp access and BX stress/support, ALS windows, final joining/separation construction and temporary power-path rating. The source band/ear 5/6/7 pin-map reconciliation remains Andi's separate update; the layout retains the current band schematic without silently swapping nets. No mounted, RF, audio, power, supplier or wearable acceptance is implied.

Generated evidence is under build/headband-layout-2026-10-25/exports/: placement-review.svg / .png / .html, drc-final.json, verification.json, final-positions.json, netlist and live/saved readback. Konnect rejected custom-shape cut-link pads during import; supported native KiCad APIs imported and placed the disposable candidate, followed by independent netlist, saved/live state and DRC checks. Only the reviewed band PCB was promoted.

The clearance/0603/USB refinement evidence is under build/headband-clearance-2026-10-25/exports/: candidate/source ERC, DRC, exported netlists, electrical-delta and geometry readback, and an aligned S3 3D render. Konnect edited the trial schematics/libraries; its incremental PCB sync rejected the existing hierarchy identities, so native KiCad updated the disposable candidate. Independent saved readback verifies every numbered pad/net, all surviving footprint anchors/UUIDs, and the unchanged stack/rules before promotion.

Applied buck/USB placement — 2026-10-26

Reviewed 2026-10-25 against source commit b18afe4, then applied after approval on 2026-10-26. The buck is rotated so the FB divider stays above/left, its input cap is below, and LX feeds the adjacent inductor/output bank to the right. USB series resistors sit beside each other with their MCU-side pads facing the S3. The CC clamp is rotated with socket-side pads below and HUSB-side pads above; C115 moves next to its VBUS pin. J101, U101, U102, BX and controls are held. The 14 approved moves match saved and live readback; the eight bridge links were reworked separately.

Coordinates use the same left-local origin and KiCad angles as above:

Ref	Applied x, y (mm)	Angle
U103	6.0, 23.5	270°
L101	10.7, 25.8	0°
C110	8.6, 22.2	270°
C113	5.5, 26.4	180°
C111 / C112 / C128	x=10.1 / 11.8 / 13.5, y=30.0	270°
R120 / R121	x=3.2, y=20.6 / 22.0	0° / 180°
R101 / R102	x=15.3, y=26.5 / 27.8	180°
D102	10.0, 35.4	90°
C115	11.2, 32.4	0°
C116	7.5, 38.7	180°

Measured pad-centre distances improve: C113-to-VIN 3.84→1.78mm, LX-to-inductor 3.54→2.23mm, FB junction span 3.52→1.40mm, nearest output-cap connection 6.29→3.51mm, and C115-to-clamp-VBUS 8.22→2.00mm. The bootstrap-to-LX leg increases from 1.94 to 2.56mm; it is a layout tradeoff, not an improvement on every metric. These are geometric distances, not routed lengths, loop inductance or electrical qualification.

Native DRC has only the four existing silk/edge findings, with no courtyard or copper-clearance violations. All pad/net assignments are unchanged. Of the other 78 footprints, eight bridge links have the separate change below; the remaining 70 placements are held. Ground vias/returns, Kelvin pickup from the filtered output, small LX copper, duplicate USB-contact escapes and plug/cable fit still need review during routing/mechanical qualification. The placement follows the layout priorities in Silergy AN_SY8301 Rev0.9A, pp.9–10; it is not a copied reference layout.

Evidence: build/headband-placement-review-2026-10-25/exports/ contains placement-review.svg / .png / .html, proposed-moves.json, placement-metrics.json, drc-proposed.json and current/proposed pad readback. Plots omit Fab text on separate render copies and add legible review labels; copper, body and courtyard geometry come from native KiCad SVG exports. The source PCB now contains the reviewed move set. No routing was added.

Mousebite bridge and net ties — 2026-10-26

JP101–JP106, JP108 and JP109 use Jumper:SolderJumper_2_Bridged symbols and two compact shared footprints, retaining their references, schematic identities and distinct left/right net names. The six signal links have 1.4 × 0.8mm copper / 0.20mm necks; 5V and GND have 2.3 × 1.0mm copper / 0.75mm necks. These replace the initial mask-covered net ties so each connection can be cut and re-soldered independently while the board is still joined. A common F.Mask opening exposes each neck and its two pads. There is no paste or fitted part; schematic and PCB exclusions keep them out of BOM and placement exports. KiCad pad group 1,2 and the local solder-mask bridge allowance describe the intentional copper join without relaxing board rules.

The board-only MB101 fixture is also in the shared footprint library. The 2026-10-26 refinement moves the 2mm slot to x=107.975–109.975mm, centred at 108.975mm between the fixed FFC and power sockets. This leaves about 0.4mm to each connector courtyard laterally. Six 0.5mm NPTH holes occupy each left fracture row and three occupy each right row, at y=92/100mm. After separation, discard both middle offcuts. Main-board anchors, outer envelope and the 8mm board spacing are held; the internal slot leaves a shallow central notch in each separated main.

The jumper centres stay at KiCad y=96. JP105/JP106 move left so all six signal links lie on the left offcut and only 5V/GND cross the right offcut. At 90°, pad 1 faces the left main below and pad 2 the right main above. Links run on F.Cu through the gaps between the holes:

Link	Temporary connection	KiCad x	Reserved width
JP101	I2C1_SCL → I2C1_SCL_R	101.2mm	0.1524mm
JP102	I2C1_SDA → I2C1_SDA_R	102.4mm	0.1524mm
JP103	PDM_CLK_R → PDM_CLK_R_LOCAL	103.6mm	0.1524mm
JP104	PDM_DATA → PDM_DATA_R	104.8mm	0.1524mm
JP105	LED_R_OUTER → LED_R_OUTER_R	106.0mm	0.1524mm
JP106	LED_R_INNER → LED_R_INNER_R	107.2mm	0.1524mm
JP108	5V_L → 5V_R	112.1mm	0.75mm
JP109	GND_L → GND_R	114.1mm	0.75mm

The minimum planned copper-to-hole gaps are 0.2738mm for signals and 0.375mm for power, satisfying the unchanged 0.25mm project floor. Hole centre pitch is 1.2mm in signal corridors and 2mm around the power corridors. Two footprint rule areas prohibit all pours/vias across the web and prohibit tracks on B.Cu/In1.Cu/In2.Cu, extending 0.5mm beyond each fracture row. All eight links are now real F.Cu tracks. Native readback checks that no via, pour, bottom or inner-layer track crosses the reserved fracture region.

JLC's capability table, checked 2026-10-26, recommends 0.5–0.8mm mousebite holes, at least 5mm perforated tabs and 2mm panel spacing. This custom electrical-tab pattern deliberately has wider hole spacing than their ordinary recommendation to retain copper-to-hole clearance. Supplier acceptance and a physical break/strain trial on 1.6mm FR4 remain open; do not assume a clean hand snap or qualified current capacity. Support the mains during separation, remove power first, discard the bridge, deburr/check isolation, then install the FFC and wire pair and retest.

Saved native readback confirms 93 footprints including MB101 / 83 nets / 359 pad-net pairs, all original footprint UUIDs and schematic paths retained, one connected outline and one internal slot. Band and parent ERC have no electrical errors. The isolated candidate has no ERC findings; the saved source currently reports one SY8301ABC library-symbol mismatch during the user's concurrent buck/library edit, which this change does not alter. The jumper change leaves all 359 schematic pad/net assignments unchanged and has the same four silk/edge findings and 289 unrouted connections. The current manual schematic baseline also has eight existing CC-net naming parity findings; these are held for a later schematic-to-PCB sync. No geometry finding or global rule change was added. The BOM export contains none of the eight jumpers.

All other PCB objects compare identically after native save/readback with the eight changed footprints removed. The user's schematic field locations and parent/standalone instance paths are preserved. Only the jumper symbols, their wire endpoints/junctions and two bridge annotations changed. No connector, regulator, leaf schematic, routing, mousebite fixture or shared symbol-library change is part of this update. Current connector and buck edits remain manual work.

Jumper evidence: build/headband-solder-jumpers-2026-10-26/exports/ contains solder-jumpers-review.svg / .png, before/after netlists, ERC/DRC and preservation checks. Konnect edited the schematic and authored the shared footprints; native KiCad supplied the unavailable pad-group/mask flags and the bounded PCB swap.

Earlier placement evidence: build/headband-placement-bridge-2026-10-26/exports/ contains placement-bridge-review.svg / .png / .html, verification.json, native netlists, BOM exclusion check, ERC/DRC and live snapshots. Konnect applied the 14 moves and edited the candidate symbols/footprints. Native KiCad supplied the unexposed net-tie pad groups and multilayer rule areas; the native schematic field editor corrected inclusion flags retained by symbol replacement. Only the validated band root/PCB and three shared footprints were promoted.

Manual revision and first power routing — 2026-10-26

Preserve Andi's five-sheet redraw, widened left main, installed right-main orientation, Pico-EZmate sockets, S3/USB/BX/control anchors and shortened web slot. J104/J204 correctly account for the 1↔10 cross-band cable, and J105/J205 for the 1↔2 power jumper. J102/J202 remain unchanged and unrouted: the ear cable's 90° fold, contact faces, final socket rotation and pin reversal need one combined continuity check. Both mic socket maps remain reversal-symmetric. External LED DIN pulldowns remain removed.

Restore JP101–JP106/JP108/JP109 to the shared exposed pre-bridged footprints above. JP1 BOOT now uses shared SolderJumper_2_Open_P1.3mm_Pad1.0x0.9mm: two 1.0 × 0.9mm rounded lands, 1.3mm pitch and a 0.3mm gap. Its nets, anchor and 180° orientation are held, with no paste, BOM or placement entry. C202 moves 0.2mm inward to x=100.8, fixing both copper/edge findings. A flag on the buck output and the right flag restored to GND_R clear the three initial ERC errors.

The manually selected SY8089A1AAC has the revised divider/Cff network. Only its group and C202 move in this pass; all other footprint anchors are held:

Ref	KiCad centre x, y (mm)	Angle
U103	109.0, 124.0	270°
C113	111.8, 122.4	270°
R120 / R121	105.8, 122.0 / 124.0	270°
C129	107.2, 122.0	270°
L101	111.3, 127.7	0°
C111 / C112	114.7 / 116.45, y=126.1	90°

Planes were established before traces as requested. Each main has a separate solid-connected GND zone on L2 and L3. Higher-priority local 3V3_L/R regions occupy L3 around the logic loads, leaving L2 as the uninterrupted return reference. All zones honour the antenna and web keepouts; the web remains free of pours/vias and bottom/inner tracks. Keep any later fast B.Cu route above L3 ground, or deliberately review its return path across a power region.

Initial F.Cu routing connects the buck's small LX node, input capacitor, divider, Cff and two output capacitors. Its input-capacitor/IC ground return has a direct front route and local vias. B.Cu carries the USB 5V feed, EN feed and initial right-board supply. The right LDO/input/output capacitors, USB power contacts, shell returns and power-socket grounds have local routes/vias. No USB data, ear feed, microphone, sensor/bus or sacrificial bridge routing is complete.

Power widths are starting geometry: 1.0mm B.Cu USB trunk with 0.4mm pad escapes, 0.6/0.7mm short USB-via joins, 0.75mm output/right-feed routes and 0.5mm LX; 0.60/0.30mm through vias are retained. Board drop, loaded temperature and transients still need qualification against the complete USB/per-ear budget. The 0.1524mm feedback routes and short 0.2/0.3mm sense/enable legs carry no ear load. These dimensions do not qualify a 2A continuous regulator output.

Saved/native and live readback cover 87 footprints, 82 nets, 74 tracks, 30 vias and six zones. Standalone ERC is 0 errors / 0 warnings. DRC has no copper/geometry errors and no schematic parity findings; 254 unrouted connections and the four existing USB/S3 silk-edge warnings remain. Physical fit, ear-fold continuity, RF/audio, load/stability and supplier acceptance remain open.

Evidence: build/headband-power-start-20261026-133618/ retains the original manual snapshot, official JLC part pages, isolated Konnect schematic edits, native footprint refresh, independent exports, readback and DRC reports. Konnect cannot refresh net-tie pad groups, so supported native KiCad refreshed the bounded footprints on a guarded copy; the saved board was reloaded and checked through live IPC before routing. Project rules were preserved.

Remaining routing plan — 2026-10-26

This section records the planning review of Andi's later manual revision. The authorised implementation below supersedes its pending actions and counts. The earlier Olimex trial was never promoted. Current live IPC and saved native board serialisations agree apart from the saved-only model-path property. The manual state is protected by signed commit 288930d, on codex/headband-manual-20261026-2156. The checkpoint includes the existing ear/project/library edits and the untracked Molex footprint, using a separate index; normal staging, main and working files were preserved. Its file hashes and copies are in build/headband-manual-checkpoint-20261026-2156/.

Keep all nine sockets, U101 S3, U104 BX and SW101–SW103 fixed. The native saved lock flags cover the sockets/S3/BX; the buttons are fixed by instruction even though their saved lock flags are clear. Hold the outline, antenna keepout and mousebite fixture. Other parts can move in small functional groups. Retain the buck near (109,124)mm; its local arrangement is now a useful starting point. Move it as a complete block only if the actual power/audio routes require it.

Proposed GPIO map

Historical 2026-10-26 allocation: the 2026-10-27 reset supersedes the LED, I2C1 and PDM rows below. The current table is in the design reference.

The routing proposal uses the module's currently spare left-edge pads for the four LED outputs and local I2C0. I2C1 moves towards the upper/front corner, beside unchanged PDM GPIO10/11. These assignments were subsequently applied to the saved schematics and PCB on 2026-10-26, preserving all other pad nets:

Function	Previous GPIO	Applied GPIO	Module pad / board position (mm)
Right outer LED, through R115	8	12	16 / (122.75,120.75)
Right inner LED, through R116	9	13	17 / (122.75,121.60)
Left outer LED, through R113	6	14	18 / (122.75,122.45)
Left inner LED, through R114	7	15	19 / (122.75,123.30)
I2C0 SDA / SCL	1 / 2	16 / 17	20 / (122.75,124.15); 21 / (122.75,125.00)
I2C1 SDA / SCL	4 / 5	8 / 9	12 / (126.35,119.70); 13 / (125.50,119.70)
HUSB320 CC_INT_N	17	18	22 / (122.75,125.85)

GPIO1/2/4–7 become spare. Preserve USB19/20, UART43/44, BOOT0/EN, PDM10/11, BX21/47/48 and IRQ38/39, and buttons41/42. Do not use the reserved strap or flash/PSRAM pins. Module pad identities were compared with Espressif's MINI-1 datasheet, pin definitions. IDF 6.1 GPIO matrix, I2C GPIO configuration and RMT GPIO selection support this peripheral assignment. The map is an engineering allocation, not proof of simultaneous four-channel RMT/audio operation. No firmware was changed.

Place R115/R116/R113/R114 in that north-to-south order beside the left module edge, with enough 0402 courtyard spacing; move the I2C pull-ups out of that bank. Put both 100Ω mic clock resistors R117/R118 close to GPIO10. They are currently near the connector ends, leaving most clock wiring before the resistors. Preserve separate clock branches and the shared mic DATA net.

Ear mapping assumption

Use 1→1 for each ear cable, with the same socket orientation relative to its mating cable and a single 90° fold. Preserve the current rail/LED contacts and both INA positions. The intended numbered band map is:

Band J102 / J202 contact	Function at matching ear J1 contact
1	Outer LED data
2–4	Local GND
5	Inner LED data
6	Local ear-bus SCL
7	Local ear-bus SDA
8–10	Monitored EAR_5V_L / EAR_5V_R

The band now has SCL/SDA on 6/7 in both saved schematics and PCB. Check actual pin 1, contact faces and every conductor in the installed fold before committing its fanout. A fold description alone does not establish the map. This supersedes the earlier proposed reversed-ear assignment; cross-band J104↔J204 remains 1↔10, and the power jumper remains 1↔2. Mic sockets remain reversal-symmetric.

Routing sequence

1. Reconcile the interfaces and finish local placement. Apply the chosen GPIO map and ear SCL/SDA correction, preserving net functions and connector poses. Keep the standard Package_TO_SOT_SMD:SOT-23-5 now used by U103; update its schematic footprint/Manufacturer field rather than reverting the manual PCB. Move the LED/PDM resistor banks and their pull-ups as above. Reserve the BX crossing corridor before filling it with power fanout.
2. Finish power distribution and local returns. Retain the broad USB 5V trunk and branch it to the buck input, unmeasured INA inputs and power socket. Complete EN→VIN and HUSB VBUS_DET. Keep each EAR_5V output separate from the upstream 5V, using its local front pour to join all three ear contacts; retain both INA positions under the 1→1 assumption. Complete the right input/LDO feed. Tie the buck output bank into L3 3V3 and add short local power/ground drops at remaining loads. Give the IC/input capacitor a direct front ground return and nearby stitching; keep LX compact and free of vias/unrelated routes. No value or topology change is proposed.
3. Route BX audio and IRQs. Keep the current module pad allocation. Use F.Cu escapes and a short B.Cu corridor above the USB body towards the lower left BX corner, crossing the existing USB/CC routes on the other layer. Stay south of the buck's LX/inductor region. The current L3 3V3 rectangle covers that corridor, so reshape it to leave continuous L3 GND beneath the bottom audio runs, with ground stitching near transitions. Preserve L2 GND beneath the existing all-front 0.219mm USB pair. Keep BCLK/WCLK/data orderly with short test-pad branches; do not add arbitrary length tuning.
4. Route the upper LED/PDM links and joined-test paths. Keep upper signals mainly on F.Cu over L2 GND. Route each mic clock after its own source resistor, shared DATA, local SEL and all paired reversible contacts. Keep the existing right mic fanout where it survives the mask cleanup. Route right LED/PDM/I2C1 functions to both their real cross-band sockets and their temporary jumper branches. Across the web, use only the reserved F.Cu corridors between the mousebites: no pours, vias or bottom/inner tracks. Preserve the eight jumper net ties and distinct L/R nets. Finish the right ear/ALS branches locally.
5. Complete I2C, controls and service nets. Route I2C0 to the left ear, ALS, BX and HUSB; I2C1 to both monitors and the right link. Bus membership and device addresses do not change with the proposed GPIO map. Use one existing pull-up pair per bus. Finish button/RESET RCs, BOOT, UART and remaining supply/test connections with local ground vias and short drops.
6. Refill and validate the actual result. Check each small functional batch, then compare fixed poses, numbered pad nets, source/library consistency and L2/L3 return continuity. Finish with ERC, schematic parity and independent refilled DRC. Four layers remain the intended solution; there is no observed reason to switch to six at this stage.

Findings to clear during those passes

At the pre-implementation snapshot, the saved five-sheet ERC had 0 findings. Refilled DRC with schematic parity reports 113 unrouted connections, 18 errors and 15 warnings, plus two U103 schematic-parity warnings. There are no reported copper short/clearance or courtyard-overlap findings in this snapshot. This is not a complete electrical, RF, thermal or fabrication audit.

• FFC mask ownership: all 12 original mask errors involved imported standalone mask polygons. Correction to the planning trial: that trial removed the polygons without adding F.Mask to the contact pads, closing the openings; its zero-error count was therefore invalid evidence. The implemented shared footprint explicitly gives contacts 1–10 F.Cu/F.Mask and +0.05mm mask expansion, removes the standalone polygons and uses 0.15mm local pad clearance so unrelated ground copper stays outside the mask opening plus the unchanged 0.09mm mask-to-copper rule. Native mask plots retain each 0.4 × 0.9mm opening envelope; pad-based expansion rounds the corners by 0.05mm. Copper, paste, MP openings, existing standalone paste apertures, numbering, nets and connector poses are retained. All six band instances are updated; the manually maintained ear PCB is outside this pass.
• Local ground connections: four starved thermals affect U103.2, both INA B1 lands and C103.2. Use suitable solid SMD connections/short local vias and direct buck returns. Five narrow connections arise where the right regulator ground patch overlaps its larger pour; simplify that border instead of reducing the global minimum connection width.
• FFC clearance regions: R118's courtyard clips the left ear keepout; its proposed source-side move removes that conflict. J204's courtyard clips the right ear keepout by about 0.05mm. Inspect the actual folded cable envelope and refine that reservation; do not move the fixed connector automatically.
• Incomplete routing / silk: three dangling power vias are unfinished feeds; eight web connections and other nets remain open. Four USB/S3 silk-edge and three 0.8mm button-label height warnings can be resolved in the final silk pass.
• Current circuit: D102 is absent from both schematic and PCB, with CC inputs routed directly to HUSB320. Preserve that manual change; the older instruction to retain D102 no longer describes this baseline.

Evidence: build/headband-routing-review-20261026-214110/ retains the hashed 56-file snapshot, live/native inventories, band/ear XML netlists, ERC, full refilled DRC, native top plot and isolated mask trial. Source CAD/library hashes are held throughout this planning pass; no routing proposal is applied.

Applied routing and geometry — 2026-10-26

The following records implementation and checks. The 2026-10-27 visual review rejected the power-routing quality; this is a WIP checkpoint for revision, not an accepted final layout. The handover supersedes any implication of layout acceptance in this record.

Signed 6f5ad7c checkpoints the complete manual working tree before changes. Signed b43538a records the GPIO/ear-contact correction, shared footprint repairs, revised bridge and smaller right outline before the routing pass. That checkpoint retains every connector, S3, BX and button pose; all fourteen held footprints are locked. U103 and its existing buck block remain at their manual positions. U201 moves to (107.6,72.0)mm, C201 to (110.9,72.0)mm and C202 to (104.5,72.95)mm, allowing the right main's top edge to move from y=64 to y=70mm. Its actual size changes from 16 × 28mm to 16 × 22mm.

The slot, eighteen mousebites and all six signal jumpers now use the geometry recorded above. All eight joined-test connections are routed on F.Cu between the holes, retaining distinct left/right nets and their intentional jumper net-tie groups. No copper plane, via or non-front track crosses the fracture web.

The placement-informed GPIO map is applied to four saved schematic sheets and the PCB. Both ear sockets now have 6=SCL / 7=SDA, with their power/LED contacts and physical poses retained. Standalone and parent ERC each have zero findings; all numbered PCB pad assignments match the fresh XML netlist. This does not establish firmware support or actual conductor continuity in the folded cables.

The buck has a direct front input-capacitor/IC ground return, EN tied to VIN, and output drops into L3. BX audio uses ordered F.Cu module escapes and B.Cu runs below the buck, with the L3 3V3 region reshaped to retain ground beneath that corridor. The original all-front USB pair is preserved. The upper LED/PDM links, right feed/LDO, measured ear feeds, ALS/I2C, controls and service nets are connected. R122/R123 move locally to make room for VBUS_DET; C115 and the BX clock test pads move out of the audio/power corridor. The mic's two 3V3 contacts have separate short drops, including a short L3 power branch; ground islands have explicit plane connections. The BX pull resistor uses a 0.45/0.20mm ground via where a 0.6/0.3mm via would not fit.

Routing trials ran on guarded build/ copies with KICAD_INRUN_FLOOR_SYNC=0, --no-fix-drc-settings, escalation disabled and the original project/rules retained. Critical copper was held while local repair passes were allowed to rework the affected nets. Independent native checks and full refilled DRC determined acceptance; the router's own completion/size summaries were not treated as acceptance. A separate final native check finds no via copper intersecting front paste apertures. Unsupported Konnect footprint clauses and schematic-sync target handling required the authorised native KiCad fallback; saved/live readback and exported connectivity verify the actual result.

The saved/live board serialisations match apart from the saved-only 3D path property. That checkpoint's 1030 tracks / 167 vias have zero DRC errors, zero unconnected items and zero schematic-parity findings under the unchanged four-layer rules. The remaining seven warnings are four USB/module silk-edge clips and three 0.8mm button-label heights, reserved for the final silk pass. This is a first routing pass; mounted fit, folded-cable continuity, temporary link current/separation, INA701 assembly, audio/RF/thermal behaviour and supplier acceptance remain physical gates.

Evidence is under build/headband-implementation-20261026-221353/: source snapshots/hashes, native sync delta, plotted mask comparison, held-pose/net checks, routing inputs/results, final refilled DRC, paste-intersection check and front/back native plots. Failed or superseded routing trials are retained separately and were not promoted as the final PCB.

Power-path revision — 2026-10-27

This revision addresses the rejected power routes from c485c3e. No KRT or other autorouter was invoked. Native KiCad operations on guarded build copies provided explicit routes, refilled pours and independent saved-state checks. KiCad was closed after the crash, with no newer band autosave and the saved source matching the handover hash. The verified candidate was then saved through native KiCad; source readback exactly matches it. There is no live-editor verification claim for this pass.

• Replace the left 5V serpentine with a direct 0.75mm spine from J105 to the buck input area. Give U106 its own 0.50mm branch and a short 0.30mm shunt-pad entry, replacing the former 0.1524mm entry.
• Move only R130, to (110.95,110.2)mm at 90°, beside the mic connector, with a local ground drop. All fourteen locked connector/module/BX/button poses and the existing buck block remain unchanged.
• Replace the HUSB VBUS_DET loop with a 0.254mm B.Cu tap into the nearby 5V supply. Remove redundant vias and the former 0.75mm loop around USB.
• Straighten the right connector feed and add a compact F.Cu 5V_R input distribution pour around the LDO and INA input. Keep EAR_5V_R downstream of the shunt and the regulator's 3.3V output copper separate.
• Use local L3 drops for the left I2C pull-ups and remove redundant 3.3V surface interconnects. Extend the 3V3_L L3 outline locally from y=132 to y=133.65mm between x=115.8 and 117.6mm, reaching the HUSB supply via and eliminating its bottom-layer feed. The BX B.Cu audio routes remain outside the power region, over the retained L3 ground corridor.
• Simplify the four module-to-LED-series-resistor escapes and remove redundant overlaid bridge-ground fragments. Retain the intentional 0.75mm bridge links, F.Cu-only fracture crossings, slot, mousebites and connector geometry.

The result has 855 track segments / 163 vias, versus 1030 / 167 at the rejected checkpoint. Summed track lengths are 77.965mm on 5V_L, 28.009mm on 5V_R and 117.434mm on 3V3_L, versus 90.874 / 45.090 / 158.028mm previously. These totals exclude pours and are not electrical resistance or current-rating measurements. The improvement is direct topology and local distribution, not merely fewer segments.

Independent saved readback preserves every footprint ID and numbered pad net, all fourteen held poses/locks, and the exact USB, BX audio, buck LX and feedback track geometry. Schematics, libraries, project rules and stackup are unchanged. No via copper intersects front paste apertures, and no via or non-front track crosses the fracture web. Refilled DRC with schematic parity reports 0 errors, 0 unconnected items and 0 parity findings under the original rules. The same seven silk warnings remain: four USB/module edge clips and three button-label text heights. Native front/back and power-region plots were visually inspected.

Evidence: build/headband-astra-20261027/ contains the original hashed snapshot, intermediate candidates, final-verification.json, final-source-drc.json, native plots and left/right before/after power comparisons. Final saved PCB SHA-256: 50e3912ff28c1ddc94dd3a63939c6583ffbc53ced91ba342f1e688c0e5aa2316. The wider signal-layout review, final silk, actual folded-cable continuity, mounted fit, bridge separation/current, thermal/audio/RF behaviour and supplier approval remain open. Physical supply-path validation is still required.

Next cleanup: current monitors and path capacity — 2026-10-27

The selected next change is INA232AIDDFR / C5447660 + Milliohm C2912774 10mΩ shunt per ear, replacing the saved INA701s at U106/U203. Use local Kelvin pickoffs, the manufacturer land patterns and I2C1 addresses 0x40/0x41. The design contract specifies ADCRANGE=1, ±2.048A nominal measurement range, SHUNT_CAL=0x0800, 62.5µA/count current and 2mW/count power. Apply the substitution as part of the next Astra cleanup.

The complete ear supply/return path now targets 1.25A continuous, allowing margin over the roughly 1.04A full-RGB-plus-sensing load. Review copper, pad/via necks, both connector ends/FFC, flex and joined-test links, plus the shared USB supply path for both ears and band loads. Existing 750mA work and the DRC/parity results above do not qualify this capacity or the replacement. This documentation update does not change source geometry, the held poses, frozen orders or firmware; fresh electrical/geometry checks and bench current/drop/thermal qualification remain required after implementation.

INA232 and signal cleanup — 2026-10-27

The updated monitor/current-target handoff is applied to the schematic and PCB. U106/U203 now use INA232AIDDFR / C5447660, and R132/R202 are 10mΩ HoYH0603-1/2W-10mR-1%-TCR50 / C2912774 shunts. The audited symbol and both footprints are in the shared libraries; see library acceptance. The shunts use the manufacturer's 1.30 × 0.92mm lands and 0.60mm gap; the provided import's smaller lands and undersized courtyard were not reused.

The schematic shows each load path above its monitor, with direct sense wires, local power symbols and ALERT NC. Left A0 is GND (0x40), right A0 is local VS (0x41), both on I2C1. Right regulator/logic consumption stays upstream of its shunt. Existing monitor UUIDs, unrelated schematic objects, GPIO assignments and cable pin maps are preserved. Konnect could not establish unique placement ownership across the valid parent/band hierarchy, so the two leaves were edited through Konnect in isolated copies, checked and promoted with exact preimage guards. Fresh standalone and parent exports/ERC then verified the actual source.

Only these existing PCB footprints move; all fourteen locked poses/locks are unchanged:

Reference	New PCB X/Y, mm	Angle
U106	104.20 / 119.45	−90°
C125	101.80 / 119.00	−90°
U203	105.90 / 75.40	0°
U201	107.60 / 71.75	0°
C202	104.00 / 71.80	180°
C205	109.00 / 76.80	0°
C206	101.90 / 77.20	0°

New R132 is at (107.05,116.00)mm, 90°; R202 at (102.20,73.90)mm, −90°. Both use separate inner-edge Kelvin pickoffs, with load current entering/leaving other land edges. The left shunt runs directly towards the ear supply zone; the right shunt sits between the input crossfeed and right ear zone. Ground and 3.3V connections use local plane drops; C205 is about 3mm from its IC via the local power/ground planes. A top-ground island opened by the local reroute has an explicit ground stitch.

No autorouter was invoked. The signal review covers the front/back routes, connector fanout, I2C buses, LED outputs, microphone/BX clocks/data, USB, controls and service connections. The deliberate cleanup replaces the I2C pull-up/module zigzags, the I2C0 SDA detour around the LED resistors, and the right-ear inner LED wiggle. Local I2C escapes move around the larger monitor footprints. The existing USB pair, BX audio, buck LX and feedback copper are unchanged by native item comparison; their functional topology is retained. Reversible mic fanout and the six sacrificial signal links remain intact.

For the revised current target, the shared B.Cu input trunk is widened to 1.5mm after its short 1.0mm entry. Its two main transitions each gain two parallel 0.6/0.3mm vias alongside the existing via. The shared F.Cu spine section is 1.25mm; per-ear branches and joined-test power/ground lanes remain 0.75mm. The right input crossfeed uses 0.9mm B.Cu and paired vias at both ends. The measured ear zones remain separate from upstream supply copper. L2/L3 planes, the fracture-web restrictions, outline, antenna keepout, stackup and project rules are preserved.

These dimensions improve the board's current paths but do not qualify a 1.25A wearable assembly. The current-path/cable review records FH34 contact derating, the selected 100mm 28AWG/1.5A Molex 369200201 jumper, and provisional 101mm GCT FFC with 0.5A conductors. The latter's nominal copper-only loop estimate is 0.111Ω with three conductors per rail. Actual current sharing, connector/contact loss, cable folds/reach, ear-flex copper, joined-tab temperature and loaded worn temperatures remain bench/fit gates.

Saved-state checks: zero standalone/parent ERC findings; zero PCB DRC errors, zero unconnected items and zero schematic-parity findings. Every numbered pad matches the exported netlist. There are 87 schematic physical components plus the board-only mousebite fixture, 80 active nets, 859 track segments and 172 vias. No via copper intersects front paste apertures; no via or non-front track crosses the fracture web. The same seven silk warnings remain (four edge clips, three button-label heights). Native front/back and monitor plots were visually inspected. Native saved readback is the evidence; no live PCB editor was open during this pass.

Evidence: build/headband-ina232-20261027/ contains snapshots, schematic/netlist comparisons, library trials, explicit native layout helpers, candidate/final DRC, final-verification.json, schematic PDF/crops and native plots. Final PCB SHA-256: 3c117086b258b5212ef3717110c4221bc291f724977627c152e71d12ffb355ff. Konnect leaves a tab-only blank line in each edited leaf; these two serializer whitespace warnings are retained rather than text-patching KiCad source. Concurrent ear geometry/tooling work is outside this revision.

Compact right board and monitor routing — 2026-10-27

Applied the visually approved placement trial and rebuilt its local routing with explicit native KiCad tracks and zones. No autorouter was used. The source was promoted only after saved readback, refilling, independent DRC and schematic comparison; the PCB editor was closed and Konnect's IPC endpoint unavailable.

The right main is 16 × 19mm, with its top edge moved from y=70 to y=73mm. The joined PCB bounds are now 37.5 × 72mm. All fourteen locked footprints keep their exact positions, angles, sides and lock state. The antenna reservation, left outline, fracture rows, slot, web and connector pin maps are unchanged.

Reference	PCB X/Y, mm	Angle	Purpose
U106	103.60 / 118.80	180°	Left monitor, analogue pins towards shunt
R132 / C125	108.30 / 119.45; 106.30 / 118.15	90° / −90°	Left Kelvin shunt and direct bypass
U203	106.25 / 75.775	0°	Right monitor, analogue pins towards shunt
R202 / C205	101.65 / 75.125; 103.55 / 76.425	−90° / 90°	Right Kelvin shunt and direct bypass
U201	109.60 / 81.80	90°	LDO between fixed ear and mic connectors
C201 / C202	109.30 / 79.00; 109.60 / 84.80	0° / 180°	LDO input/output bypass
R201	110.00 / 77.40	0°	Mic-select pull above LDO
C206	108.50 / 87.00	−90°	Ear bulk cap clear of the cable keepout
TP105 / TP106	101.50 / 129.60; 101.50 / 132.10	0°	Accessible 3V3/GND pair
TP107 / TP108	103.90 / 134.20; 106.20 / 134.20	0°	BX BCLK/WCLK probe pair

The monitor arrangements follow TI INA232 Figure 8-5: shunt beside IN+/IN−, straight inner-edge Kelvin branches, bypass immediately beside VS/GND, and digital signals on the opposite side. Main current enters and leaves the other shunt-pad edges. Ground returns have local plane vias; the left VS via sits beneath the IC, outside paste and clear of retained rear signals. C126 also has a short local ground drop.

The right LDO has 0.30mm courtyard separation from each fixed FFC. Its input and output caps connect locally. A new broad 5V_R region on L3 feeds the right shunt through paired 0.6/0.3mm vias, with another pair beside J205. The low-current LDO branch taps this upstream supply independently of the shunt. The reshaped 3V3_R region leaves the left-side 5V corridor wide; L2 ground remains continuous. This replaces the earlier 0.9mm rear crossfeed. Sampling horizontal sections of the filled 5V corridor every 0.01mm over y=75.5–85.2mm gives a minimum contiguous width of 1.817mm. Equivalent samples of the left/right measured-ear pours give 0.90mm / 1.5225mm. These are bounded geometric checks, not whole-path current or thermal tests. The 1.25A per-ear target and complete assembly qualification remain open.

Right I2C, LED and mic trunk routes are rebuilt around the new blocks while retaining the fixed mic socket's reversible local fanout. The left I2C0 SDA branch uses L3 to avoid cutting through the shunt power feed; its L2 ground reference is retained. TP107/108 use short taps from the existing BX clock trunks; the adjacent I2C0 SCL branch clears their probe lands. UART test points remain together under the module. USB, buck LX/feedback and BX data copper match the preceding source item-for-item. Schematics, libraries, net assignments, GPIOs, board rules and stackup are unchanged.

Validation on the refilled saved candidate and promoted source: 0 DRC errors, 0 unconnected items, 0 schematic-parity findings. The same seven existing silkscreen warnings remain. Native readback checks all pad nets against a fresh source netlist, all footprint UUIDs/hierarchy, locked poses and absence of via copper intersecting component paste. The source remains 88 footprints / 80 nets, with 842 tracks, 176 through vias, ten copper-zone objects and two board FFC component keepouts. No physical/current, cable, optical or mounting gate is closed.

Evidence is under build/headband-rework-20261027/: source snapshot and hashes, candidate, fresh netlist, verification.json, DRC and native front/back/inner plots. The accepted trial is under build/headband-floorplan-20261027/. Final PCB SHA-256: ba4fda735f1fd802eb30925d6b4289bc10de9512f23ffeaa088bd8cb9df1d823.

Routing reset after manual review — 2026-10-27

The left-side rear routing, BX audio paths, several passive placements and redundant ground fanout remain unsatisfactory. Repeated local repairs around existing tracks are not the next approach. Preserve Andi's manual buck circuit as a functional block; it may move or receive justified local tweaks. Keep the locked module, BX, switches and connectors, mechanical outline, antenna reservation and fracture geometry. Preserve subsequent manual edits in recovery snapshots before any rework. Other routes, via locations, unlocked placements and application GPIO assignments may be reconsidered together.

Layout conventions for that rework:

• Place unlocked component origins on a 0.25mm grid where practical. Route vertices on 0.025mm; connect exactly to footprint pad centres even when their package geometry is off-grid. Do not add tiny corrective segments merely to reconcile two grids.
• Prefer 45° via escapes followed by clean 45°/orthogonal runs. Align vias with their associated pads where it makes the escape clearer. Use space beneath packages when it is mechanically and electrically appropriate; avoid open vias in paste lands and preserve actual antenna/component keepouts.
• Ground pads served by sound filled ground copper do not also need individual track spokes. Retain useful stitching/return vias, including the existing module-end row by default. Its positions were not the objection; redundant trace branches were. Verify the refilled connectivity after removing them.
• Use deliberately shaped pours for high-current distribution and local supply blocks. Plan signal corridors and return copper together, instead of forcing signals around a stack of overlapping wide tracks.
• Rotate and regroup parts to suit the whole circuit. Trial a horizontal left shunt, input from the right-side supply and measured output towards the ear, with the INA rotated/repositioned to preserve short independent Kelvin paths.
• Reconsider application GPIO ordering before routing the I2C, LED, PDM and BX bundles. Preserve native USB and console requirements, boot/strap restrictions and module-reserved pins; validate any proposed mapping before schematic edits. The existing BX audio copper is eligible for rerouting, not a protected asset.
• Place test points as short, accessible taps after the main routes are planned. Do not make the signal paths bend around an arbitrary probe-pad arrangement.

Circuit simplification, now applied: remove C115, the 100nF 5V bypass retained after its original D102 clamp was removed; remove optional ear-feed reservoirs C126/C206 (4.7µF each). They are not the INA VS bypasses or regulator stability capacitors. The current ear master has 10µF entry C55 and distributed LED decoupling. Retain INA C125/C205, actual regulator capacitors and, at that checkpoint, USB-input C116. C116 is subsequently removed on 2026-10-31 to reduce VBUS capacitance/inrush; the buck and LDO stability capacitors remain. Loaded cable/ear transient behaviour still needs measurement.

Read-only review evidence: build/headband-routing-reset-review-20261027/ holds the committed board, saved manual board and a native IPC copy of the live board. Saved and live footprint/copper inventories agreed at capture. The manual delta moves R202/R201 and changes right-side routing plus left 3V3 routing. A separate trial removes 30 module-end GND track segments without moving vias; refilling adds no opens relative to the captured manual baseline. That baseline itself has three outstanding connections (right ALS SDA and two ground islands), so this is not a clean-board validation. Source CAD is unchanged by this review.

The subsequent pre-routing reset review records snapshot bc993cc, completed capacitor removals, the exact proposed keep/remove boundary, placement, GPIO changes and large-pour treatment. Those placement/GPIO/routing changes were approved and are applied in the following record.

Approved manual routing reset — 2026-10-27

This supersedes the earlier routed checkpoints. Andi approved the reset review, including further removal of surplus joint vias. Recovery commit bc993cc preserves her manual state; 9d5dccc records the three capacitor removals and review preparation.

The schematic and PCB now use I2C1 SDA/SCL on GPIO10/11, PDM CLK/DATA on GPIO9/8, right outer/inner LEDs on GPIO7/6 and left outer/inner LEDs on GPIO5/4. GPIO12–15 are spare. I2C0, native USB, console, BX and button assignments are unchanged. Device addresses, FFC mapping, monitor calibration and peripheral allocation are unchanged. The controller sheet uses short labelled MCU stubs and the existing resistor blocks for the remapped nets. Firmware remains read-only.

All fourteen locked footprint poses, footprint identities/hierarchy, mechanical outlines, antenna reservation and rules are preserved. So are the eight manual buck component poses, R101/R102, all 42 buck copper items, all 32 USB copper items, and the 20 temporary bridge track segments. No autorouter was used. Source changes were made with Konnect for the schematic and supported native KiCad APIs on guarded PCB copies while the editor was closed.

The horizontal left shunt and rotated INA now have separate sense connections from the inner shunt-pad ends. Source resistors form the upper bank, with their MCU-side pads facing the module. Upper signals follow an ordered rear-layer fanout around the shoulder. BX audio/control, I2C, CC, controls and service connections are rebuilt; the module-end ground-via row no longer has redundant fanout tracks. Ground pads use the filled plane where it provides connectivity. The right regulator/monitor block is retained in the compact board envelope.

Small routing-driven adjustments from the reviewed placement include rotating the LED resistors/R131, exchanging the two clock-resistor positions, moving the right INA and its bypass down 0.5mm, moving R130 to (108.5,108.5)mm, the left ALS bypass pair to y=119mm, C114 to (115.5,131.75)mm, TP104 to (133.5,136)mm TP108 to (109.75,134.25)mm and R131 to (101.75,137.75)mm. These are unlocked components; the buck and USB resistor positions are unchanged. Source footprint pad geometry remains exact; nominal component origins follow the 0.25mm placement grid.

Pour/return changes:

• L2 remains the separated continuous GND_L/GND_R reference; there are no L2 signal tracks. The right L3 power-region outlines remain unchanged.
• Left L3 3V3 uses the reviewed rectangle ending at y=132.25mm. The freed lower area is ground. Short L3 I2C/CC escapes, BX IRQ runs and local supply taps provide crossings; L3 is therefore not an uninterrupted ground plane.
• The left measured-ear pour is the reviewed simple rectangle. The new 5V outer-layer regions replace the old wide-track constructions. The upper feed widens into the retained buck input interface; the rear link ends at y=132.5mm. The USB crossfeed uses a 1.5mm-wide region and paired 0.6/0.3mm transitions. The right shunt and power connector also use paired 0.6/0.3mm vias. Narrow HUSB/LDO taps and Kelvin traces carry only local supply/sense current.
• Front ground regions use solid pad connections. Redundant joint/obsolete return vias were removed; three isolated front ground regions at BOOT, the left ALS and mic ground have explicit local plane vias. The final via check finds no copper intersecting any front paste land.

Saved verification: 499 track segments, 164 through vias; zero copper errors, zero unconnected items, zero schematic-parity findings with all-track-errors enabled. Eight silkscreen findings remain: seven existing edge/text-height findings and the right INA/ear-connector silk overlap. This is not a silkscreen/fabrication release. Standalone and parent ERC are clear. Netlist comparison, locked/retained-object checks and native via/paste checks are recorded in build/headband-final-routing-20261027/. The source project/rules files are unchanged. The review page and native layer plots are derived outputs in that same directory.

The 1.25A continuous per-ear target, shared USB input, cable/connector current sharing, thermal/drop behaviour, buck transients, assembled audio timing and RF/mechanical acceptance still require physical qualification. DRC connectivity does not establish those limits. Inspect the new layer views before fabrication; manual routing does not by itself establish layout quality or acceptance.

Manual layout and pin-map update — 2026-10-29

Andi manually revised the routing, passive/service placement and schematic presentation after 5cdbf5a. The current interface changes are:

Function	Previous GPIO / module pad	Current GPIO / module pad
I2C0 SCL	17 / 21	15 / 19
HUSB320 CC_INT_N	18 / 22	26 / 26

I2C0 SDA remains GPIO16 / pad20. R107 now pulls SCL up and R108 pulls SDA up; their values remain 4.7kΩ. GPIO17/18 are unused and marked no-connect. GPIO15 is no longer spare; GPIO1/2/12–14/17/18/40 remain available. Other peripheral assignments, I2C addresses, connector mappings and component values are unchanged. GPIO26 is valid for the selected MINI-1-N8; the N4R2 PSRAM variant is incompatible with this allocation. The current tables and firmware integration boundary are in the design reference and handoff.

The revision removes C124 and the BX clock test points TP107/TP108. An initial check caught an unmarked GPIO18 and a remaining single-layer BX_BCLK via; Andi's next save resolved both. Subsequent agent changes only replace the schematic GPIO annotation through Konnect and reconcile the maintained docs. The manual PCB and all other schematic edits remain byte-identical to that save.

Final saved-board evidence under build/headband-manual-fix-20261029/:

• 551 track segments / 162 vias; fresh native refill and full-track DRC report zero errors, zero opens and zero schematic-parity findings. Eight existing silkscreen warnings remain; none is a new routing exception.
• Standalone band and parent hierarchy ERC have zero findings.
• Native checks find no pad/net mismatches or via/paste overlaps. The outline is valid and unchanged, and L2 has no signal tracks. Refilling the disposable copy preserves tracks, pad assignments and footprint poses.
• All 61 fast tests and just check pass. Source hashes confirm that validation did not modify any CAD or library file. The annotation edit changes no netlist connectivity.

The 27 October browser review is a historical snapshot. Current source files and this record own the updated state; the earlier visual counts and service probe positions must not be read as current. Physical/cable/current/audio/RF qualification and final silkscreen work remain open.