Headband rigid-board setup¶
Selected 2026-10-25 for the rigid, electrically joined L/R assembly/test board. The separate ear and microphone flexes have their own fabrication requirements. This is a layout starting profile, not a fabrication release or a quotation.
Stack¶
Use the 1.6mm nominal, four-layer JLC04161H-7628 option, without an A suffix. This is the standard 7628 stack also listed under JLC's no-requirement option. Outer copper is 1oz and inner copper 0.5oz; retain the selected ENIG finish. Six layers are a fallback only if four-layer routing proves impractical.
The current JLC stack table gives:
| Layer | Material | Thickness | Relative permittivity |
|---|---|---|---|
| F.Cu | Copper | 0.0350mm | — |
| Dielectric 1 | FR4 7628 prepreg | 0.2104mm | 4.4 |
| In1.Cu | Copper | 0.0152mm | — |
| Dielectric 2 | FR4 core | 1.0650mm | 4.6 |
| In2.Cu | Copper | 0.0152mm | — |
| Dielectric 3 | FR4 7628 prepreg | 0.2104mm | 4.4 |
| B.Cu | Copper | 0.0350mm | — |
The copper/dielectric entries sum to 1.5862mm. KiCad additionally models 0.01524mm solder mask above each copper face, so its stack-derived board thickness is 1.61668mm. Select the manufacturer's 1.6mm order option; do not interpret the CAD sum as a request for a custom thickness. Mask epsilon-r is 3.8. Dielectric loss tangent 0.02 is a CAD placeholder, not a supplier-guaranteed loss specification. CAD colours are illustrative.
Start with signal / GND / GND-and-power / signal. Keep L2 continuous under the USB route; preserve L3 ground under fast bottom-layer routes and use local power regions without breaking those returns. Pull all layers back from the planned separation line, apart from deliberate sacrificial surface links. The mousebite fixture now enforces no pours/vias on all four layers and no non-front-layer tracks through the bridge, with 0.5mm pullback beyond both fracture rows. F.Cu links pass between the NPTH holes; all eight bridge links are now routed. The 2026-10-26 checkpoint establishes separate L/R ground zones on L2/L3 and local 3.3V distribution regions on L3, plus initial buck/USB-power/right-LDO routes. Subsequent B.Cu signal routing must retain an appropriate L3 return. The steel band is under the frontmost edge, clear of the rear antenna overhang.
Stored rules and defaults¶
The band .kicad_pro, .kicad_pcb and fresh .kicad_dru replace the inherited
polyimide stack and flex-only constraints. Ear files retain their flex profile.
| Setting | Value |
|---|---|
| Copper clearance / minimum track / minimum connection width | 0.127mm |
| Ordinary signal routing width | 0.1524mm |
| Minimum via diameter / drill | 0.45 / 0.20mm |
| Minimum via annular ring | 0.125mm |
| Default via diameter / drill | 0.60 / 0.30mm |
| Copper to board edge | 0.30mm |
| Copper to unrelated hole | 0.25mm |
| Via hole-to-hole floor | 0.20mm |
| Solder-mask expansion / minimum web / mask-to-unrelated-copper | 0 / 0.13 / 0.09mm |
| Silk text height / stroke | 0.8 / 0.15mm (minimum height updated 2026-11-02) |
These conservative routing floors sit above the advertised multilayer track/space capability. The 0.45/0.20mm via avoids JLC's listed small-via surcharge boundary. No microvia or blind/buried-via process is selected; use through vias only and check via types during layout review. The official rigid capability table was checked on 2026-10-25. Before release, additionally review component-hole spacing ≥0.45mm, plated annulus ≥0.15mm, plated slots ≥0.50mm, NPTH ≥0.50mm, non-plated slots ≥1.0mm, and silk-to-mask-opening spacing ≥0.15mm. These component/outline checks are not all encoded in the layer-floor rules. Use the stricter specific supplier rule where it applies.
Netclasses are Default, USB, POWER_5V and POWER_3V3; unrelated
PCIe/reference-clock classes are removed. 5V_* and GND_*
default to 0.75mm routing; 3V3_* defaults to 0.30mm. These widths are routing
preferences, not a current-capacity certification or a prohibition on short
pad escapes. Use planes/wide copper for the input and ear feeds, and review
the new 1.25A continuous per-ear target, temporary links, via sharing and
neck-downs during layout. This replaces the 750mA target; existing checks do
not establish the higher current capacity. Review the shared upstream path
for both ears plus band loads as well as each individual branch.
USB pairs¶
| Segment | Positive / negative nets |
|---|---|
| Socket to R102 / R101 | USB_LINE_P / USB_LINE_N |
| R102 / R101 to WROOM MCU pads 14 / 13 | USB_MCU_P / USB_MCU_N |
The socket-side pair is global; MCU labels are sheet-local, so their exported
net names include the hierarchy path. _P and _N are the final suffixes on
both segments so KiCad can recognise the differential pairs. D101, the external
D+/D− clamp, is removed for this prototype; its former socket/line segments
are merged. The subsequent manual revision also removed D102; CC1/CC2 connect
directly to HUSB320 in the current schematic and PCB. The 22Ω resistors retain distinct MCU-side nets.
The USB class matches only these pair-name patterns. With F101 removed, input
VBUS is part of 5V_L; the obsolete USB_VBUS power-net pattern is removed.
Target 90Ω differential on F.Cu over L2 and B.Cu over L3. The saved 7628 stack is symmetric: both outer-to-inner dielectrics are 0.2104mm with the same outer copper, so the accepted geometry is mirrored for the rear section. Andi's JLC calculator result on 2026-10-25 for standard JLC04161H-7628, 1oz outer / 0.5oz inner copper, Differential Pair (Non coplanar) with solder mask, signal L1, no top reference, bottom reference L2 and 5mil edge gap is 8.61mil trace width. This is 0.218694mm width / 0.127mm gap; the initial USB class rounded width to 0.219mm. The later manual routing uses 0.2032mm / 8mil traces, also stored in the current USB netclass. The 7 November review confirms these match the previous checked source and were not changed by the latest manual edits. Do not describe the current 8mil geometry as the exact 8.61mil calculator result. The previously discussed 8.32mil result belongs to 3313A and is not used here. These are calculator-derived routing dimensions, not a measured fabricated impedance. Keep nearby same-layer pours away from this non-coplanar model, minimise pad escapes and vias, and retain a continuous ground return. The 2026-10-31 rear-USB revision uses 0.218694mm width and about 0.1313mm coupled-run gap, four signal vias and a B.Cu pour keepout. Filled-copper checks verify L2/L3 reference coverage outside the intentional transition antipads and at least 0.6366mm same-layer pour setback. The local fanouts are not continuously coupled. See the saved geometry and route lengths.
The saved INA701 footprint has a 0.200mm minimum copper gap, including between shunt and logic lands, and needs no copper-clearance exception. The 2026-10-27 selection supersedes INA701 and its INA745A fallback with INA232AIDDFR + C2912774 10mΩ shunt. The substitution is applied with audited DDF leads, manufacturer shunt lands, Kelvin pickoffs and revised current copper under these rules rather than reusing the WCSP footprint. The monitor contract owns range/scaling, I2C addresses and the distinction between measurement range and qualified path capacity.
The HUSB320 lands now have a 0.150mm minimum copper gap. The local G-Switch USB footprint trims only the merged GND lands at their peg-facing ends, giving approximately 0.263mm copper-to-NPTH clearance. Neither change relaxes the global rules. Manufacturer geometry and the derivative are recorded in the library audit.
Verification boundary¶
The saved five-sheet and parent-hierarchy ERC/netlist checks cover schematic connectivity; native KiCad readback covers the stack, class definitions and effective class selection. The rough placement now has an outline and footprints: native DRC checks those against the stored rules, with zero errors, zero unconnected items and zero schematic-parity findings after the 2026-10-27 power-path revision. Four overhanging-footprint silkscreen findings and three button-label text-height warnings remain. The revised mousebite geometry and all eight pre-bridged links are routed; physical separation trials and supplier acceptance remain unfinished. The initial power-routing quality was rejected despite those checks. The explicit power-path revision replaces the offending feeds under unchanged rules, preserves all locked poses, and retains zero errors/opens/parity findings. Signal review/cleanup is also applied; the original handover is historical evidence. Final impedance, current/thermal behaviour, supplier assembly approval and the mounted USB/antenna/BX behaviour remain separate checks.
The INA232/signal revision uses a 1.5mm main B.Cu input trunk, a 1.25mm shared F.Cu spine section and parallel supply vias at the main transitions. Per-ear branches and temporary power/ground bridges retain 0.75mm lanes; the right input crossfeed is 0.9mm with paired vias. Short pad/transition entries remain narrower. Project clearance, stack and netclass defaults are unchanged; these are explicit route dimensions, not a thermal qualification of the complete path.