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Ear pair and JLC quote pipelines

Removable moat infill (2026-10-27): the current cleanup extends aw-ear-fab with rail-free supported/ variants that retain blank moat material on twelve 0.8mm laser tabs per ear through assembly and shipping. Top-level Gerber/BOM/CPL files select those variants. Apply both the exterior Edge.Cuts and the required interrupted laser_depanel.gbr; the stroke does not specify kerf. The existing variants/ boards retain finished B-only geometry for independent clearance, connectivity and CAM validation, and for ear-renders. The 25 October frozen record remains a previous pre-order candidate and is not changed.

All ear workflows use the requested ear-flex stack: nominal 0.12mm finished polyimide flex, 0.5oz copper per side, white coverlay, black silk and ENIG. The saved CAD model now uses that nominal stack; actual white-coverlay construction may be thicker and needs supplier confirmation.

The current approved upload set is build/ears/aw-cpl-corrected-2026-10-29/, measuring 104.989862 × 71.896165mm for the pair. Its matching Gerber/BOM/CPL files are an assembly-data revision of the complete AW build from committed source 6865354: Gerbers and BOMs are byte-identical; only AW placement angles change. BUILD-PROVENANCE.json binds the corrected CPLs to the canonical build and its manifest. Finished and shipping variants pass DRC with zero errors/opens, electrical/parity/ CAM checks and seven artifact tests. The three electrode wire lands and coverlay openings are removed, with the obsolete rear-tape notches filled. Read ORDER-NOTES-pair.md before upload; the covered-electrode record lists retained warnings and validation. The approved outline and nominal 0.12mm / 0.5oz CAD stack remain unchanged.

CPL rotation corrections

The ear exporter reads the source schematic's JLCPCB_CORRECTION field, using KiKit's X; Y; rotation syntax. This workflow currently supports rotation only: X and Y must be zero; nonzero translations, malformed values and non-finite numbers fail export. An absent/blank field means zero correction. Rotation is added to the native package angle, counter-clockwise positive, modulo 360°. It changes the CPL only, never the board geometry, Gerbers or render placement. Other project exporters have separate contracts; this is ear-export support.

U1 AW96105DNR / C5125883 has 0; 0; -90: 90° clockwise, confirmed against the EasyEDA numbered-pad layout and Andi's JLC placement adjustment on 2026-10-29. It follows the same physical part into the right ear as U1001. The present standalone/pair files therefore export U1 at 190° and U1001 at 139°, replacing 280°/229°. Other rotations and all coordinates remain unchanged. Applied values appear in each assembly report's placement_corrections. The corrected CPL already includes this adjustment.

The rotation record documents the comparison, source field and assembly-only revision checks. The existing aw-covered-2026-10-27 renders still depict the unchanged physical layout; their original input manifests remain intact.

AW-equipped rail-free workflow (2026-10-25): use just aw-ear-fab <installed-round-tracks-plugin> <fresh-output> for the baseline/AW refinement. It derives rounded left/right working boards and finished left, right and pair variants, with no process rails, tooling, fiducials or frame. The pair must measure less than 109mm wide. Each variant has matching ESPurr-{left,right,pair}-Gerbers.zip, -BOM.csv and -CPL.csv together at the output root, plus detailed notes and manual rear-connector lists. There are 101 front factory parts per ear; C9 is removed and J1 remains manual. The first-build sensor selection is AW96105DNR / C5125883, JLC Extended, replacing the unresolved AW93205 selection with the same pinout/land pattern; see the selection record. This command checks B-only moats, the AW per-hand pin maps, all physical pad terminals, actual CAM/coverlay and package transforms. The older LED-only artifact verifier is not used to certify these outputs. The previous AW96105 checked output is build/ears/aw96105-rounded-2026-10-25/: pair dimensions 104.989862 × 71.896165mm, 0 DRC errors and 0 opens in each variant. Run its independent artifact/negative controls with just test-aw-ear-fab build/ears/aw96105-rounded-2026-10-25.

AW/B-only working master (2026-10-25): use just right-ear <fresh-output> or just rounded-right-ear <installed-round-tracks-plugin> <fresh-output> for the completed AW right-ear routing review. Those commands run the AW-specific checks and produce PCB/previews, with no manufacturing package. The older pair/panel/quote pipeline below retains its LED-only population and two-moat contracts; it is not an AW production pipeline.

Historical LED-only workflow

The remainder of this guide describes the retained LED-only pipeline and its checkpoint contracts. Use aw-ear-fab above for the current AW/B-only source; the old population/two-bridge checks are expected to reject it.

Historical LED-only order choice (2026-10-23): use the frame-free variants/pair/ combined L/R board, at most 109mm wide, or the separate left/right variants. JLC supplies its own process rails/carrier and moat support. The older framed 119mm carrier described below remains an intermediate/comparison output; do not upload it for this order. Generate rounded exports with just rounded-ear-quote <installed-round-tracks-plugin> <fresh-output>. Request nominal 0.12mm / 0.5oz per side, white coverlay, black silk and ENIG. Frozen exports retain their recorded CAD stack. Three independent rear electrodes with manual wire pads replace the two covered anchors.

The left master is the only input. The immediate review outputs are native KiCad boards: just panel <fresh-output> snapshots the saved design, generates a right ear with real package pin identities and constructs the mixed carrier. just ear-quote <fresh-output> additionally writes Gerbers, drills, BOM and CPL. Everything derived stays beneath build/. These are quote/CAM-review inputs, with a separate incomplete production verdict. No supplier upload, order or physical acceptance is implied.

# Native boards first; no full manufacturing package.
just rounded-panel /path/to/com_github_mitxela_kicad-round-tracks build/ears/review-next
just test-ear-routes build/ears/review-next
uv run --script scripts/hw.py test arcs
uv run --script scripts/hw.py ear preview build/ears/review-next
# Omit rounding with: just panel <fresh-output>

# Optional full manufacturing export to a different fresh directory.
just ear-quote build/ears/quote-next
just test-ear-quote build/ears/quote-next
# Optional second full run and physical comparison (timestamps/UUIDs differ).
just ear-quote build/ears/quote-repeat-next
uv run --script scripts/hw.py ear compare build/ears/quote-next build/ears/quote-repeat-next

The default output is build/jlc-quote/. Start with its README.md and the four top-level ZIPs: ESPurr-panel-Gerbers.zip, ESPurr-pair-Gerbers.zip, ESPurr-left-Gerbers.zip and ESPurr-right-Gerbers.zip. Each ZIP includes its drill files. The framed panel's BOM/CPL are in quote/; frame-free versions have their own matching BOM/CPL in variants/pair/, variants/left/ and variants/right/. Never mix CPL files between variants: their origins differ.

Frame-free outputs use the finished ear contours and open moat cutouts, with no rails, fiducials, tooling holes, support tabs or separate laser file. They are bare-fabrication/supplier-panelisation inputs; PCBA still needs a carrier and moat supports. The pair contains two distinct designs, one L and one R; five pairs/panels mean five of each ear. Each variant is built from the same run's freshly generated units and checks numbered pads/nets, poses/sides, connectivity, DRC, actual outline/copper/coverlay Gerbers, drill/paste counts, and BOM/CPL agreement. One native outline per ear is required, including its two final moat cutouts. No source project or prior build becomes the input.

Use a fresh destination for every run. Existing nonempty output, paths outside build/ and symlinked path components are refused. A failed run has FAILED.json and no acceptance manifest. A successful run gets manifest.json only after the exit-path source hash check. The manifest binds source, tooling, sourcing policy, reports and every generated artifact to hashes. just ears <output> stops after the pair; just panel <output> stops after the carrier. Neither partial stage advertises a fabrication package.

Dependencies are KiCad 10, its compatible Python/pcbnew, uv/Shapely/Gerbonara, and the existing KiKit environment. KICAD_CLI and KICAD_PYTHON use the workflow overrides. The current right-ear routing does not invoke KRT or change authored project constraints. It uses native KiCad objects and a bounded visibility shortest-path search against actual pads, expanded coverlay openings, existing traces/vias and the final ear outline. Front GND drops use off-pad, tented 0.6/0.3mm vias. Actual exported coverlay is checked even for the native board-only stages; those two audit Gerbers per board are not a quote package.

The 2026-10-23 LED-only native review checkpoint was build/ear-library-sync/current/:

  • left/espurr/espurr-ears/espurr-ears.kicad_pcb: LED-only left copy.
  • right/espurr/espurr-ears/right.kicad_pcb: completed right ear.
  • panel/espurr-led-pair.kicad_pcb: supported assembly carrier.
  • review/: saved-copper views of both panel faces, right ear and the three reported routing problem areas; yellow highlights data copper.
  • manifest.json: source/tooling/artifact hashes, route quality, DRC, connectivity, coverlay and carrier checks.

The left input includes signed checkpoint 2dd2d8a: the baseline/tip pour cleanup, followed by Andi's D68 routing simplification. Its 332 straight segments and 108 vias remain the editable source; all data copper is 0.1524mm. The later printed-outline update restores alignment notches on silk and matches the shared library artwork. Exact input hashes are recorded in the completion manifest. The hard width and clearance floors remain 0.127mm by design. Build copies use native EAR_DATA fillets at a 0.25mm radius setting, retaining their exact unrounded inputs and hashes alongside the rounded output. No component is moved by rounding. See the dated trial and limits. --source-ref <local-commit> pins the tracked design files to a committed revision, while retaining required local assets. Input hashes identify that revision; separate live-source hashes detect changes to the working design during generation. The generator never restores or overwrites parallel edits.

These paths identify disposable historical output and may have been cleaned. The checkpoint archive retains the dated evidence; frozen inputs live under manufacturing/orders/. No existing build directory is implicitly current or refreshed by a later source change.

Physical reflection and connectivity

The native generated right preserves each electrical package's physical pad numbers, local pad geometry, net assignments, population and assembly side. LEDs/capacitors remain F.Cu; J1 remains B.Cu. The source contour, two moat cuts, two permanent bridges and zone outlines are reflected. T1/T2/T3 manual wire pads and their independent experimental electrodes are retained and excluded from assembly output. Removed or native-DNP support parts are absent from the manufacturing copy; retained DNP symbols do not enter BOM/CPL.

A same-sided LED reflection permutes pad positions. Copper therefore cannot simply be reflected onto the unchanged pin numbers. The generator explicitly replaces right routing, routes against actual pads, and verifies the saved result. All generated data traces use 0.1524mm, matching the left master's EAR_DATA routing width. The former forced 0.254mm / 0.35mm-clearance autorouter pass is retired. Of 67 inter-LED links, 66 stay on the front and 62 are single straight segments. Small bends at D13, D30, D54 and D61 avoid real pad/coverlay obstacles. The D57–D59 links are direct front traces, with no data vias. D1's connector feed approaches DI without the old acute return bend.

The only inter-LED rear crossing is D68→D69, retaining two off-pad vias: a front trace across the inner region divides the 5V pour. Each rear connector data feed uses one transition, giving four data vias total. A short front power connection reinforces D30's corner pad, and explicit rear GND connects J1.2–4 to an existing ground via outside the connector courtyard. These are checked against actual filled-copper connectivity rather than inferred from net names. J1 GND uses solid zone contacts; J1.8–10 retain 0.254mm rear power links. Data-width, layer/via count, branch/loop, route length and acute-angle checks inspect fresh saved native geometry. Focused negative controls exercise fat traces, redundant vias, sharp corners, spurs, missing transitions and changed physical pad/pose/side data.

The generated right uses the held front +5V pour to supply front power pads. New vias are tented on both faces. Ground-via relocation checks the actual 0.254mm stub width; overlapping same-net holes are consolidated only with their connections retained. The authored 0.25mm drilled-hole gap, 0.5mm via-land-to-edge limit and all project constraints remain. Independent DRC and exported coverlay checks reject introduced clearance, mask, neck-width or required-net opens. Printed outlines intentionally clip at mask openings: cosmetic silk_over_copper warnings are retained only with saved mask-subtraction enabled. Other silk findings still fail. CLI Gerber export explicitly uses --subtract-soldermask.

Footprint fields now follow each real package's native rotation and movement; reflecting their absolute positions separately put the right connector's reference across its pin-one mark. Printed body outlines and LED corner notches are retained as recorded in the silk update, superseding that part of the earlier DFM cleanup.

Worldsemi's V6 datasheet, page 2 identifies DO=1, GND=2, DI=3 and VDD=4. The library zero pose is rotated 180 degrees from that illustrated top view. The generator checks numbered local pad positions, not just a reflected union of copper. J1 preserves the source FH34SRJ physical numbering: 1 outer data, 2–4/MP GND, 5/6 unused SDA/SCL, 7 inner data, 8–10 +5V. Every right pin retains its original function; there is no assumed cable reversal.

Both ears retain J1.1 → D1–D48 and J1.7 → D49–D69, with centre D69 last. Right winding reverses in a front view while logical chain indexes are retained. LED-map.csv records the panel references and chain indexes explicitly. Right panel references add 1000 (D1→D1001, J1→J1001). Visible reference strokes are moved clear of their own silk artwork after renaming, so the longer J1001 text does not collide with its pin-one dot. Net namespaces LEFT_ and RIGHT_ keep all unit nets, including power/ground, electrically separate.

Checks use fresh native readback, schematic XML pin partitions, direct CLI DRC and an independent Shapely graph of filled copper, pad polygons, tracks and vias. Projected overlaps between layers do not count as connections. Saving/reloading before filling is mandatory: filling newly assembled native objects can leave stale connectivity. Numbered pad/track nets are checked before and after save because KiCad can propagate nets onto conflicting copper.

KiKit 1.8.1 appendBoard encountered a KiCad 10 SWIG lifetime failure after removing footprint-contained edges. Panel assembly instead uses native object duplication, preserves removed outline proxies until saved, and checks every panel component/pad against its transformed input. The panel's native Edge.Cuts is the outer assembly sheet, with both moat pieces per ear retained as temporary supports. Interrupted unit and moat perimeters live on the named laser_depanel manufacturing layer (User.45), with a dedicated Gerber. Reference artwork remains on non-fabrication drawing layers.

Panel and quote contract

The current master packs to 119 × 86mm, with the ears nested and rotated −170° / 139°. This retains a 2mm margin beyond all four 5mm rails and remains smaller than the earlier 119 × 90mm layout. The preceding 119 × 80mm candidate optimised too close to rail/fiducial features. The bounded joint search uses conservative 5-degree/2mm raster correlation followed by exact-contour refinement to 1 degree / 0.05mm; it does not establish a global optimum.

Corrected 2026-10-19: JLC's 2mm means spacing between board outlines, not 2mm routed slots around the units. The current minimum spacing is 2.031039mm. Surrounding panel material stays in place, with no added carrier web allowance. The outer laser paths have twelve 0.8mm uncut support tabs per ear. Each ear's long moat piece has twelve more tabs and its short moat piece has four: 28 tabs per ear, 56 per panel, all 0.8mm wide. The moat pieces stay in place through assembly to brace the centre island; snip their tabs and remove them afterwards. Both permanent ear bridges remain. Retained support pieces and inter-ear scrap are copper-free; solid copper is confined to the process rails and the ear circuits. Tab gaps lie on straight contour sections, avoid pads by at least 0.3mm and are verified independently. The four 5mm rails remain intact; units have an additional 2mm clearance beyond their inner edges. This is a project handling margin, not an additional JLC board-spacing requirement. The generator also requires at least 2mm from ear outlines to drilled tooling-hole edges and 1.5mm to fiducial coverlay-opening edges. Saved native feature positions and actual exported drill count are checked.

Four 2mm NPTH tooling holes, four 1mm global fiducials and one local fiducial associated with each ear are retained. There are exactly four tooling holes; the six fiducials are undrilled copper marks. One corner's tooling/fiducial positions are offset 5mm. Fiducials have 2mm coverlay openings and no paste. Rail copper is isolated from both ears on both copper layers. Fiducials have 1mm clearance from their copper land edges, giving 1.5mm-radius rail exclusions. Tooling holes have 0.5mm clearance from their drilled edges, also 1.5mm-radius exclusions. Actual exported copper distances are recorded for both faces; unit marks use opposite rails. Both rail pours are solid, confirmed against their actual exported copper layers as well as saved fill. The scrap between ears remains uncoppered: JLC's copper-border requirement applies to the process rails. rail-copper-CAM.svg exposes the rail copper for inspection; the ordinary coverlay preview labels the holes, draws the rail boundary and shows fiducial lands at their actual 1mm diameter inside 2mm openings.

laser_depanel.gbr contains interrupted laser centrelines, exported from the named native layer. Its 0.05mm plot stroke does not specify kerf. The Edge.Cuts Gerber defines only the outer sheet. The dedicated laser file also contains the tabbed moat outlines; the original cutouts are not open during assembly. Both files are necessary machining inputs. JLC must confirm their file-role mapping and laser process before production; the Gerber job and generated notes identify them explicitly. No V-score, mouse bites or wide routed unit-perimeter slots are generated.

Native panel DRC sees the intact assembly sheet. Standalone ear DRC and a separate check of actual saved panel copper against each separated unit contour cover the eventual laser edges, including 0.3mm copper / 0.5mm via-land clearance. Generated +5V/GND zones are explicitly clipped 0.3005mm inside the separated ear contours and outside the moat plugs because source pours depend on native edge/cutout clipping. Other zone definitions are retained and their actual fill is checked. The source PCB still has its two original moat cutouts. Native laser readback and actual exported Gerber must match all paths and tab gaps. The CAM previews overlay the exported laser geometry in red.

The exact 79/119/240mm automation rule and ≥70mm other dimension are retained from Andi's order requirements. The current JLC panel guide corroborates 5mm rails, 2mm spacing, 0.7–1mm laser bridges, asymmetric fiducials/tooling and local unit marks. Its general panel-size range does not establish that exact automation restriction. JLC's FPC tips also recommend 119mm width. The panel guide was rechecked 2026-10-19 against Andi's supplied diagram. JLC must review the final service-specific panel, laser tab and carrier arrangement.

Quote two-layer, nominal 0.12mm/0.5oz polyimide flex, white coverlay, black silk and ENIG. The saved CAD model uses 0.12mm nominal including coverlay/adhesive; confirm actual available construction/tolerance, especially thicker white coverlay. Five panels is a useful quote assumption, yielding five left/five right ears. No metal stiffener is assumed; if added, revisit JLC's 3mm spacing and special stiffener slots. No stiffener geometry is emitted. Rear adhesive coverage is now specified separately in rear tape artwork and exported as psb_tesa8854.gbr.

Factory assembly is front only: 138 LEDs, 48 × 100nF 0402, six 1µF 0402 and two 10µF 0603 entry capacitors, 194 parts total. Rear J1/J1001 remain manual assembly. The front stencil has 664 apertures and no rear stencil is supplied. manual-assembly.csv retains the rear connector identities separately. BOM.csv and CPL.csv have exactly matching designator sets; copper anchors, outline footprints, tooling and fiducials are excluded.

C55 uses Andi's explicit C96446 source selection: Samsung CL10A106MA8NRNC, 10µF, 25V, X5R, 0603, listed Basic in the JLC entry checked 2026-10-19. The part policy resolves its missing source MPN for exports without substituting another LCSC part. It records the old source 10V/X7R descriptive fields as superseded by this selection. The earlier Murata C2959727 quote-only candidate is retired. An explicit different source MPN/LCSC is never silently replaced.

Output and acceptance boundaries

The quote/ folder contains Gerbers.zip, BOM.csv, CPL.csv, manual-assembly.csv, LED-map.csv, QUOTE-NOTES.md, SVG previews and CAM-checks.json. Raw Gerbers include both copper/coverlay/silk faces, front paste, Edge.Cuts and the dedicated laser file, plus separate PTH/NPTH Excellon files, maps and job metadata. Drills are counted against actual vias/tooling; exported mask, paste and outline are parsed independently, including via-hole-to-opening distances. CPL uses millimetres, the panel lower-left origin, X right/Y up and native KiCad angles. Library-specific rotation offsets require JLC's placement preview.

Production release remains INCOMPLETE while supplier handling/support, FFC continuity and placement preview remain open. Full reports are retained; the source's unused electrode open is reported separately from required LED connections. Rerouted right power paths still need current/drop/thermal qualification against the 2026-10-27 1.25A continuous per-ear target, including connectors and FFC; see the current-path contract. Historical 750mA calculations/checks retain that scope and do not establish the higher capacity. Frozen order inputs are unchanged. Passing software checks does not prove flex fit, loaded LED operation or supplier acceptance.

Earlier validation evidence

The 2026-10-18–19 quote and routing checkpoints retain earlier populations, DRC counts, output directories, reproducibility results and build cleanup history. Later native routing, pour cleanup and printed-outline records explain subsequent changes. Use each run's manifest and reports for its actual findings.