Headband JLCPCB quote inputs¶
2026-10-31: WROOM-1-N16R8, 35 × 73.5mm joined board. Routing and supply-pour cleanup are complete, with clean source ERC/DRC/parity. The exact module is LCSC C2913202. Earlier MINI-based packages remain historical inputs. The new WROOM placement still needs supplier preview confirmation; no rotation correction has been guessed.
Generate from the latest saved headband with just band-quote build/headband-quote-YYYYMMDD.
Use a fresh output directory. The command copies sources into work/, refills and
checks that copy, then exports CAM and assembly files. Unit and panel copies
use the same 1µm fill accuracy, recorded in fill.json; the saved source rules
remain unchanged. Source CAD and libraries
are hash-checked on success and failure. No routing, placement or source fields
are changed. This workflow covers the joined rigid L/R board only, not ear or mic flexes.
Upload espurr-band-manifest.json records the full revision, exact inputs and download filenames;
separate payload/file hashes verify the particular exported bytes.
espurr-band-<hash>-Production.zip bundles the three upload files for downloading;
extract it before uploading the individual files to JLCPCB.
Order settings¶
The 2026-11-02 artwork includes a solid 5 × 5mm rear QR placeholder. Apply the marking settings and processed-qrb inspection when ordering; a local solid square is intentional and is not a generated barcode.
- Rigid FR-4, four layers, nominal 1.6mm, standard JLC04161H-7628.
- Outer copper 1oz, inner copper 0.5oz, ENIG.
- Green solder mask and white silkscreen on both faces. The saved band stackup and native renders match these colours as of 2026-11-01.
- Assemble top side only. On 2026-10-29 the quote portal required Standard PCBA for LSM6DSV16BX and ESP32-S3-MINI-1. The current single-assembly export is only 35 × 73.5mm and lacks a carrier; it does not satisfy Standard PCBA's minimum 70 × 70mm and edge-rail requirements. Use the KiKit two-set panel workflow for Standard-PCBA quote files.
- Keep the joined, electrically connected test fixture intact through assembly. Separation uses the supplied routed slots and NPTH mousebite holes, no V-cuts. Do not substitute a two-design panel or remove the temporary bridge before test.
- Normal tented vias; no filled/capped via-in-pad process is requested.
- The board stack includes explicit mask thickness in CAD; order nominal 1.6mm, not a custom thickness derived from that sum.
Assembly checks and sourcing¶
The BOM excludes copper-only BOOT/bridge jumpers, test pads and the mechanical mousebite fixture. Their copper and holes remain in the Gerbers/drills. BOM and CPL designators match.
Four missing source metadata entries are supplemented in the quote only:
| References | Quote selection | Reason |
|---|---|---|
| U101 | ESP32-S3-WROOM-1-N16R8 / C2913202 | Exact 16MB flash / 8MB PSRAM module; guarded by value and WROOM footprint |
| U102 | HUSB320-BA000-QN12R / C7471906 | Exact selected controller |
| C201, C202 | CL05A105KA5NQNC / C52923 | 1µF, 25V, X5R, 0402; exceeds the specified 16V rating and shares existing C103/C204 selection |
C102 now uses its saved source selection, 22µF 0603 / C59461; the old 10µF fallback is removed. The fitted population is 66 parts per headband set.
R122/R123 use 200kΩ 1% 0402, UNI-ROYAL 0402WGF2003TCE / C25764 (Basic),
selected on 2026-10-29 and saved in both schematic and PCB properties.
parts-audit.csv records every selected part and metadata source. Catalogue
presence does not establish live stock.
CPL positions use native KiCad pad-bounding-box midpoints, millimetres with the
same auxiliary origin as CAM and positive Y upwards. Rotation is native KiCad
counterclockwise plus the source schematic's JLCPCB_CORRECTION offset,
normalised to 0–360°. The field uses KiKit's X; Y; rotation syntax; this exporter
supports rotation-only corrections and rejects nonzero X/Y instead of silently
discarding them. U103, U106, U201 and U203 each carry 0; 0; 180, following
Andi's JLC placement-preview findings on 2026-10-29. The PCB package poses stay
unchanged. Applied corrections are recorded in the manifest. No generic package
rotation corrections are guessed. Inspect every placement in JLC's preview before ordering,
particularly the ESP32 antenna overhang, asymmetric connectors, USB, HUSB320,
INA232, ALS and IMU. The pad midpoint is an initial matching coordinate, not a
verified pick-up centre. Use assembly-front.svg and the board's numbered pads
as the orientation reference; the supplier may require centroid/rotation adjustments.
Evidence and remaining gates¶
manifest.json, geometry.json, erc.json, drc.json and cam-checks.json
record the exact sources, population, drill/slot inventory, checks and hashes.
The exporter rejects ERC findings, DRC errors, opens, parity mismatches and
unexpected warning types. The current source has no DRC warnings. The exporter
retains its explicit silkscreen-only allowance for future quote runs and records
any such warnings. Drill readback permits only the 0.000501mm rounding tolerance required by
KiCad's 0.001mm decimal Excellon output, with one-to-one hole matching.
CAM includes all four copper layers,
both masks/silkscreens, top paste, outline and separate PTH/NPTH drills.
These are quote inputs, not a supplier-approved production release. Assembly
preview, mousebite/slot acceptance and current/thermal/mechanical qualification
remain separate checks. The manifest uses QUOTE_FILES_GENERATED_PREVIEW_REQUIRED.
Two-assembly panel¶
The current two-set KiKit carrier is 75 × 91.5mm, with one copy rotated 180°, 6mm top/bottom rails, 3mm board gaps, 5mm side rails and 2.25mm side gaps. Saved F.Fab package envelopes give a 3.4mm minimum component-to-other-board gap and 3.65mm minimum inter-copy body gap, including module/USB overhangs. This is a 2D envelope check, not a 3D collision test. One two-up panel contains 132 fitted placements and produces two complete headband sets.
Standard PCBA requires at least 70 × 70mm overall, rails at least 5mm wide and
fiducials. A panel should include tooling holes and three non-collinear fiducials.
JLC's panelisation service adds fiducials/tooling holes when rails are selected;
their acceptance of this stepped outline and component overhangs must be checked.
The separate just band-panel <fresh-output> command now generates this
carrier with KiKit, twelve frame tabs and a central bridge with mousebites at
both ends, tooling holes, fiducials and duplicated
BOM/CPL. See the panel guide for its verified geometry and
manufacturing-copy treatment of RF clearance and copper pours. The original
single-board exporter still outputs one set. One two-up panel contains two
complete headband sets.
JLC rail/fiducial guidance and panelisation guidance.
Supplier references checked 2026-10-31: JLC CPL requirements, BOM/CPL preparation, assembly capabilities, LCSC C2913202, LCSC C7471906, LCSC C52923.