Hardware design reference¶
Detailed selections and interface requirements supporting PLAN.md. Keep the root plan brief; update design detail here. The initial headband schematic is captured; provisional dimensions/startup sequences are not validated hardware. Working rules live in AGENTS.md; checkpoint evidence lives in the ear archive and quote pipeline.
Ear flex design¶
Geometry and placement¶
The left source has 69 WS2812C-2020-V6 LEDs: D1–D48 outer, D49–D68 inner loop, D69 centre. The outer order starts at the short-edge/base corner and runs clockwise viewed from the front; D13 is the apex. The two electrical chains contain 48 and 21 LEDs, with the centre last on the inner chain.
Preserve the current D1–D69 and J1 poses, external contour and electrode definitions. The 2026-10-25 B-only pocket adoption removes bridge A, fills the small corner pocket, rounds the new island corner to R1mm and reroutes the inner LED feed through B. B is the island's sole permanent bridge. Non-LED support parts/capacitors may move within an authorised design task when useful for routing; compare against the latest saved design, not an old fit or routing snapshot. LED reference fields remain hidden.
The baseline curve uses a fitted quadratic with short native Bezier transitions into the held rounded corners. Its maximum change from the earlier trace is 0.37905mm; the side edges, bounds and moats are held. Front 5V and rear GND zone boundaries follow this baseline.
The 69-LED fit record retains the
frozen selection and later manual inner-loop refinements. just ear-fit-69-current
reproduces the held poses/guides. The moat guide
links the historical two-slot contour and the saved-board
SVG export workflow. Old population/routing counts belong to the archive.
The physical frame/fabric and 1:1 fit checks remain authoritative mechanical gates. Original Illustrator coordinates are points, 25.4/72mm per unit; registered fit geometry uses millimetres. Do not turn the foam path directly into Edge.Cuts. V2 back fabric needs fold-over allowance not yet specified by the reference overlay. Verify tip strain, shaping curvature, component/bend clearance and diffusion on the actual assembly.
LED power, data and decoupling¶
- Use WS2812C-2020-V6, with 5mA per full-duty colour channel as the working current coefficient. The 2026-10-27 continuous design target is 1.25A per 5V ear path, replacing 750mA. At that coefficient, 69 pixels at full RGB draw about 1.035A before other loads; allow a few additional mA for ear sensing and roughly 20% margin. This is a target for review/qualification, not established capacity or an unconditional operating limit. Recheck both supply and return copper, neck-downs/vias, connectors, FFC and flex at 1.25A; historical 750mA checks and frozen order inputs retain their original scope.
- Drive data directly from 3.3V GPIO. No 5V level shifters or hardware LED power gating. Validate VOH/LED thresholds, cable/ground margin, reset/brownout, cold boot and unpowered/disconnected cases. Damping/protection still need review.
- Fit the existing 27 LED capacitors: local/shared 100nF groups, distributed 1µF parts and entry C55 10µF. C9 and C56 are removed. Shared decoupling departs from the per-LED application example and needs switching/transient qualification.
- Prefer a short front pad-to-local-via GND drop into rear GND over a detour to an existing LED via. Verify actual filled-plane contact and drilled-hole to coverlay clearance. Preserve later manual fixes.
- Retain the cleaned rail pours: obsolete support/connector/touch-feed recesses are removed and rear GND follows the bottom perimeter through native edge clearance. Existing side-electrode relief stays. Do not reintroduce old holes or recesses from archived geometry.
- Retain the printed package outlines and LED alignment corners, with covered anchor artwork on Fab and mask openings subtracted from plotted silk. This supersedes the earlier Fab-only body-artwork decision; see the printed-outline record. C55 uses Andi's explicit C96446 selection: Samsung CL10A106MA8NRNC, 10µF, 25V X5R, 0603, JLC Basic when checked 2026-10-19. The export policy resolves its missing MPN; the former Murata quote-only candidate is retired.
Normal firmware must begin black, establish a safe USB/per-ear budget, then start current-limited animation. Enforce the 70% blue ceiling through saved settings, overrides, diagnostics and dithering. Recovery+test defaults to off. See the complete-device power policy.
Requested ear-flex stack¶
The canonical ear request is two-layer polyimide flex, nominal 0.12mm finished thickness, 0.5oz copper per side, white coverlay, black silk and ENIG. Use 18µm nominal copper per side for electrical estimates, with actual supplier thickness/tolerance recorded separately.
The saved ear and empty parent placeholder now use the same 0.120mm nominal CAD stack: 18µm F.Cu, 25µm PI core, 18µm B.Cu and 29.5µm white coverlay/adhesive on each face. White coverlay may make the actual finished flex thicker; this split is a convenient nominal CAD/render envelope, not a supplier-confirmed laminate schedule. Confirm the actual finished construction, copper tolerance and bend behaviour with JLC before release. Rear Tesa adhesive and local stiffeners remain additional.
The 2026-10-27 stack update records
the source change and verification. Frozen inputs and retained older builds
keep their original stack and hashes. Generated order notes share the current request through
ears/fabrication.py.
Flex, electrodes and connector support¶
Three independent B.Cu electrode regions have covered copper-only net anchors: T1 short
side /TOUCH_SIDE_A, T2 long side /TOUCH_SIDE_B, T3 tip /TOUCH_TOP. Each
0.8mm anchor lies wholly inside its electrode, with no coverlay or paste opening;
all are excluded from BOM/CPL. The former oval manual wire lands are removed.
The current schematic assigns these nets to AW96105 inputs; the corresponding
PCB connections are routed. All three electrode anchors are represented
in the schematic. See the
experimental electrode record. Through-fur sensing is untested.
Keep bridge B and current side relief. Bridge A is removed and the bottom-left sensor pocket is applied. Sensor feed qualification and electrode keepout conversion remain open. Do not restore the older two-channel/raw-touch or Qvar geometry as instructions.
Support rear J1 locally without covering front LED pads. Keep the rounded baseline and no connector notch. Preferred entry setback is at most 5mm, with 10mm absolute maximum; the current pose is held. Support material, side, thickness, actuator access, FFC strain relief and physical pull/bend tests remain open. Earlier opposite-face support measurements need rechecking against the live 69-LED geometry before choosing a solution.
Stiffeners use dedicated named manufacturing layers with closed 0.05mm
documentation outlines and filled production geometry where the supplier requires
it. Record material, side, thickness, contour, bend/transition clearance and
filename per region. Keep annotation text outside PCB geometry and production
Gerbers. Rear adhesive output is named psb_tesa8854, separately from
Edge.Cuts. The rear tape artwork defines the current coverage,
connector access and export contract; supplier process acceptance remains open.
Ear connector and physical mapping¶
Use Hirose FH34SRJ-10S-0.5SH, ten contacts at 0.5mm pitch, back-flip/ dual-contact, on B.Cu with the current local footprint/pose. J1 is the only assembled rear part; LEDs and capacitors remain F.Cu. The covered electrode anchors are copper features, not assembled components.
The connector guide owns the physical contact map and held connector pose.
The generated right preserves those functions with actual package pad numbers;
its front-view winding reverses while chain indexes remain explicit in LED-map.csv.
No address-strap population swap applies to this prototype.
Verify actual pin 1, contact face, entry direction and every conductor through each board/cable assembly. Cable-type labels do not establish continuity; full contact-order reversal can short GND/+5V. Confirm removable FFC mating thickness separately from PCB/stiffener thickness. User fit estimates are about 30mm per ear FFC, 170mm cross-band span and 360mm usable band, excluding the silicone-covered end kinks; these are not cable specifications or measured drop.
AW96105 routed prototype¶
The first-build master selects U1 AW96105DNR / C5125883, JLC Extended, in the shared 1.8x2.1mm DFN-10 footprint, with U2 XC6206P332MR-G / C5446. All added components are on F.Cu. C2 is a local 1uF input bypass; C1 is the shared 1uF regulator-output/AW reservoir; C5 is the AW's 100nF bypass. C1/C2 use the existing Basic C52923 / Samsung CL05A105KA5NQNC, 0402, 25V X5R. Redundant C3 is removed. Keep each ear's 3.3V output local and verify retained capacitance under bias. This supersedes the earlier AW93205 choice for sourcing. The AW96105 manufacturer datasheet confirms the same numbered pin map and 0.4mm-pitch DNR land pattern; the existing symbol pin geometry and footprint are reused with the explicit AW96105 fitted Value/MPN, supplier ID and datasheet. Placement/routing are held. See the selection record.
The current ear schematic and PCB use J1.5 LED_DAT2 / J1.6 SCL / J1.7 SDA, following the I2C pin swap after Andi's manual connector fanout revision. T1 uses U1.9 CS4, T3 U1.8 CS3 and T2 U1.7 CS0. U1.6 CS1 and U1.3 CS2 are marked spare; U1.10 INT_N is unused. The part's documented 7-bit I2C address is 0x12. The AW is front-side above the regulator, with its three sensing contacts facing the short-edge corridor. Local power, I2C and electrode feeds are routed; series resistors, protection and driven-shield selection remain open. There is no ear IMU. The current I2C transition placement puts both vias below U1, with C1/C5 lower and C1's ground via clear of the rear runs. The routing checkpoint records the initial numbered-pad/net and exported-coverlay evidence. The lower-moat refinement trims the baseline-side lip, smooths the island kink and lowers the support block; it also checks actual mirrored package fit and local escape feasibility. The band interface now uses the same 5 inner-data / 6 SCL / 7 SDA map. The connector guide and headband maps below own the current cable contract. Actual board/cable continuity still needs qualification before connection.
Prefer short narrow sensor feeds with clearance from power/data and other electrodes on both layers. A front-side feed over its own rear electrode is the same electrical node; a long overlap with a different electrode adds unwanted inter-channel capacitance. Prefer lateral separation and short crossings over parallel overlap. Awinic recommends CS traces no wider than 0.1mm, below this project's current 0.127mm fabrication minimum; resolve that departure when routing.
The placement checkpoint records saved geometry/connectivity evidence before the later routing refinement. Existing LED-only order exports predate this master and remain historical inputs. Qualify through-fur response/drift with LED traffic, USB noise, movement, humidity and the worn assembly.
Headband electronics¶
Design entry¶
The initial five-sheet band schematic includes GPIO/peripheral allocation, component selection and shared library additions. Each ear interface carries two LED data lines on J1.1/5 and I2C SCL/SDA on ear J1.6/7 for the local sensor. The electrodes stay local to each ear; they have no direct connection through J1. The connector guide owns the physical ear map; older raw-touch/Qvar sketches do not define it.
The selected microphone, right LDO and current GPIO/cable maps are below. Verify the actual cable mappings before fabrication, and settle mounting/separation geometry and the antenna keepout during placement. Use the rigid stack below and confirm its USB geometry before routing that pair. Ear physical qualification remains a release gate. The first PCB outline and rough placement is saved; routing review, microphone-flex design and firmware implementation remain open.
Use the shared espurr/symbols.kicad_sym (Symbols:) and
espurr/footprints.pretty (Footprints:) for new band library assets. The
band library audit records physical pin/pad
maps and provenance; retain the existing parent/standalone project hierarchy.
Construction and mounting¶
Design rigid FR4 left/right mains as one electrically connected assembly/test PCB, then separate them and install the cross-band FFC plus wire power pair. Separate short, straight plug-in microphone flexes are individual assemblies. The schematic is populated. The PCB placement implements the provisional envelopes as one joined outline, with perforated breakaway tabs and pre-bridged PCB solder jumpers for joined testing. The power-path revision replaces the rejected serpentine feeds and simplifies local distribution/fanout without autorouting. Locked placements, pad nets and project rules are preserved; refilled DRC has zero errors, opens or schematic mismatches. The subsequent INA232 and signal cleanup is also saved. The 1 November silkscreen pass adds white ink, connector polarity/function labels and bridge identifiers; physical qualification remains. The Astra handover retains the rejected checkpoint and recovery evidence. These dimensions still need a mounted fit check.
- Use nominal 1.6mm / four layers, JLC04161H-7628, 1oz outer / 0.5oz inner copper, ENIG, green solder mask and white silkscreen on both faces. This replaces the older 1.2mm / six-layer preference; six layers are a fallback if routing becomes impractical. Start with signal / GND / GND-and-power / signal, retaining a return plane beneath any fast bottom-layer route. The rigid-board rule record owns the actual stack dimensions, routing defaults and outstanding USB calculation.
- The steel band is 5mm wide, with roughly 45mm flat mounting length; PCB width may reach 40mm if needed. The broad-foot left sketch is currently 35 × 45mm, plus 6.5mm rear WROOM antenna overhang; about 41.5mm overall in that direction. The right main is now 16 × 19mm, shortened from 16 × 22mm by placing its regulator and bypass capacitors between the fixed ear and mic FFCs. The original manual outline was 16 × 28mm. Mounted fit remains unverified. Label front/rear in component-side concept views.
- The approved compact placement moves USB 2.5mm forward: its shell front is about 7.5mm behind the PCB front; check plug access on the assembly, with the cable exiting straight down when worn. Application buttons and RESET are rearward.
- Put the entire S3 antenna section beyond the rear PCB edge, with supported solder lands and the module's RF keepout clear of steel, housing and wiring. The steel band runs under the leftmost/frontmost edge of the boards, clear of the rear antenna overhang; antenna-over-steel is not the proposed mounting geometry.
- Put LSM6DSV16BX directly on the lower/front corner of the left rigid main, coupled through head → steel band → hard-mounted PCB → BX. No separate BX flex/socket. Retain the comfortable existing band pressure region without loading the IC, bowing the PCB or introducing loose/soft joints in that path. Review sensor stress, local support, screw/clamp separation and hot spots.
Use routed slots/mousebite tabs, with planned sacrificial F.Cu links through the gaps between the holes. Eight pre-bridged solder jumpers join 5V, GND and all six cross-band signals while preserving separate left/right net names. Their exposed copper necks can be cut individually and re-soldered for isolation tests; there are no fitted parts or paste openings. The bridge record owns the provisional two-tab/two-fracture-row geometry, hole clearances and 0.1524mm signal / 0.75mm power lanes. The jumper footprints contain copper; the connecting traces are now routed. Keep planes/vias and non-front-layer routes out of the separation region. Qualify the temporary power path against the chosen test load, and verify supplier acceptance and separation strain. Remove power, support the mains, separate/deburr, discard the bridge and inspect isolation, then fit cables and retest. Joined operation does not qualify the final cable assembly.
Parts and responsibilities¶
Use G-Switch GT-USB-7010AO / C963413, the orange 16-contact USB 2.0
receptacle, for J101. GT-USB-7010ASV / C2988369 is the black alternative;
both are JLC Extended parts when checked 2026-10-25. Their manufacturer drawings
share the contact, peg and shell-slot pattern used by
Connector_USB:USB_C_Receptacle_G-Switch_GT-USB-7010ASV.
The AO is rated 5A and the ASV 3A; the HUSB320 sink/current policy still limits
this design to the advertised USB current, at most 3A. Use the G-Switch footprint
rather than assuming the USB4105 land pattern is identical. The
library audit
records the dimensions and outstanding shell-solder/stack checks.
Prefer JLC Basic parts for ordinary passives, keeping the required value, tolerance, package, voltage and effective capacitance. Exact MPN/Manufacturer/LCSC properties are populated for the following parts; classifications were checked against the linked JLC catalogue on 2026-10-25 and need rechecking at order time.
| Value / requirement | MPN | LCSC / JLC classification | Quantity |
|---|---|---|---|
| 22Ω, 1% | UNI-ROYAL 0402WGF220JTCE | C25092, Basic | 2 |
| 100Ω, 1%, LED data and PDM clock branches | UNI-ROYAL 0402WGF1000TCE | C25076, Basic | 6 |
| 4.7kΩ, 1% | UNI-ROYAL 0402WGF4701TCE | C25900, Basic | 4 |
| 10kΩ, 1% | UNI-ROYAL 0402WGF1002TCE | C25744, Basic | 6 |
| 100kΩ, 1%, including R120 | UNI-ROYAL 0402WGF1003TCE | C25741, Basic | 3 |
| 200kΩ, 1%, R122/R123 HUSB320 straps | UNI-ROYAL 0402WGF2003TCE | C25764, Basic | 2 |
| 22kΩ, 1%, R121 | UNI-ROYAL 0402WGF2202TCE | C25768, Basic | 1 |
| 22pF, 50V, C0G, 5%, C129 | FH 0402CG220J500NT | C1555, Basic | 1 |
| 100nF, 16V, X7R, 10% | Samsung CL05B104KO5NNNC | C1525, Basic | 10 |
| 1µF, 25V, X5R, 10% | Samsung CL05A105KA5NQNC | C52923, Basic | 2 |
| 4.7µF, 16V, X5R, 10%, 0603 | Samsung CL10A475KO8NNNC | C19666, Basic | 1 |
| 22µF, 6.3V, X5R, 20%, 0603 | Samsung CL10A226MQ8NRNC | C59461, Basic | 3 |
This table covers 41 selected Basic passives, including the 200kΩ straps selected on 2026-10-29. Other quantities follow the saved 2026-10-27 netlist after C115/C126/C206 removal; the two divider resistors and C129 were rechecked against JLC's official listings on 2026-10-26. Prefer 0402 ordinary passives, with 0603 the normal maximum; use a larger case only for a specific electrical/mechanical need. The band has no remaining 0805 capacitors. R117/R118 use the same 100Ω 0402 part as the LED data series resistors. The existing right-side XC6206 / C5446 is also Basic. R122/R123 now use 200kΩ C25764 in source CAD. The quote guide records the selected IC and right-LDO capacitor metadata supplements and the Standard PCBA restriction reported by the quote portal. Buck output capacitor bias data and qualification limits are below. Catalogue availability and classification do not establish supplier acceptance of this assembly.
| Left main | Right main |
|---|---|
| ESP32-S3-WROOM-1-N16R8, 16MB flash / 8MB PSRAM | No duplicate MCU/RF section |
| USB-C, HUSB320 CC/current detection | Cross-band power/signal terminations |
| SY8089A1AAC main buck, 3.327V nominal | XC6206P332MR-G / C5446 local 5V→3.3V LDO |
| INA232 + C2912774 shunt beside left ear connector | INA232 + C2912774 shunt beside right ear connector |
| LSM6DSV16BX for head motion and full contact audio | Matching PDM microphone flex |
| Left LTR-F216A ALS and PDM microphone flex | Right LTR-F216A ALS |
| Two application buttons, separate RESET, open GPIO0/GND BOOT jumper | Required filtering, support and test points |
Selected 2026-10-27: one INA232AIDDFR / C5447660 and one Milliohm HoYH0603-1/2W-10mR-1%-TCR50 / C2912774 per ear 5V feed. This supersedes INA701AYWFR as primary and INA745AIRELR as sourcing fallback. The saved schematic and PCB now fit INA232A at U106/U203 and 10mΩ shunts at R132/R202, with audited shared-library assets and explicit Kelvin routing. The applied cleanup records placement and validation. Firmware integration remains separate. See ear-current monitors and scaling for the pin map, new addresses, Kelvin routing and calibration contract. Keep right logic/LDO consumption upstream of its measured ear branch. No whole-device current monitor is required without a concrete requirement.
Use Lite-On LTR-F216A / C2971916 on both mains, fixed address 0x53, 1.7–3.6V supply. Verify its six-pin land/paste map and optical openings; hair, fur and ear LED spill affect readings. Polling avoids a cross-band INT line. Select gain/integration/range policy and window correction from its datasheet; a typical current figure is not a worst-case right-LDO budget.
Keep C123/C203 as local 100nF ALS bypasses. The 2026-10-29 manual revision removes left bulk provision C124; the right 1µF C204 remains. The Lite-On application circuit (section 6, printed p.20) shows 100nF plus 4.7µF. Validate the selected local and shared rail capacitance on the assembled board. Extra BX bulk C122 and main-board microphone-connector bulk C127/C207 are removed; retain the BX's two local 100nF caps, each microphone flex's local 100nF and C103's EN/reset timing capacitor.
Use XC6206P332MR-G / C5446, SOT-23-3 (1 GND, 2 OUT, 3 IN), for right logic. The manual revision uses 1µF / 16V 0402 input/output capacitors; retain these pending final part/bias and regulator-stability checks. Its load is the right mic, INA232 and ALS; reserve 25mA for initial power/thermal budgeting rather than treating the regulator's 200mA rating as available wearable load. Check actual load, sequencing and rail behaviour during qualification.
The manual buck replacement is SY8089A1AAC / C479074, with 2.2µH APV ANR3015T2R2M / C6364793, 22µF input C113 and two 22µF output capacitors, C111/C112. The reference is 0.6V; R120=100kΩ / R121=22kΩ gives 3.327V nominal, up from 3.245V with 220kΩ/49.9kΩ. Both are Basic 0402 1% parts. C129=22pF C0G / C1555, also Basic 0402, bridges R120. Silergy AN_SY8089A1 Rev0.9 recommends 100kΩ/22.1kΩ and 22pF for its 3.3V transient-response example; 22kΩ uses a Basic value with a small nominal voltage increase. The IC supports 2.5–5.5V input and needs no bootstrap capacitor. C110 and C128 are removed.
The arrangement follows Andi's adaptation of the
Olimex ESP32-S3-DevKit-LiPo Rev B.
That reference names SY8089AAAC; the fitted A1 variant has its own 1.5MHz
datasheet. Keep its pin-compatible symbol's historical library name
Symbols:SY8089AAAC, with the actual A1 MPN in the instance.
The selected CL10A226MQ8NRNC has about 9.77µF at 3.3V on Samsung's typical 25°C DC-bias curve. The two output parts provide about 19.5µF typically, or 15.6µF with a further −20% nominal tolerance allowance before temperature/ageing. The former SY8301 three-capacitor/>22µF rationale is superseded. The curve is typical, not a guaranteed minimum; qualify temperature, ageing, RF-burst/load transients and stability on hardware. The A1 application note recommends >10µF input/output ceramics and gives a 2.2µH / 22µF or 2×22µF output combination for 3.3V. Nominal table values do not prove stability at actual effective capacitance. The selected inductor's 1.5A rating also requires peak-current/transient and temperature qualification.
C116, the additional 4.7µF/16V USB-entry reservoir, is removed on 2026-10-31
by prototype choice to reduce directly connected VBUS capacitance and inrush.
Retain C113 at the buck input, C111/C112 at its output, and each LDO's local
input/output capacitors. Removing C116 does not establish USB inrush compliance;
the complete directly connected load still needs qualification. Optional ear-feed
reservoirs C126/C206 are also removed; the ear master retains entry C55 and its
distributed decoupling.
USB VBUS feeds 5V_L directly; F101 is removed. Budget cable and board drop
at the loaded USB input. Verify
startup, inrush, MCU/RF bursts, stability and thermal margin on the actual assembly.
For this prototype, defer a dedicated inrush limiter and accept plug-in
qualification on the USB sources/cables actually used. The last nominal-capacitance
inventory predates the buck/input-capacitor swap and must be refreshed before
inrush qualification. USB source overcurrent
protection, with the source's own trip level/delay, is the accepted prototype fallback.
The external D+/D− clamp D101 is also removed by prototype choice; socket-to-series
resistor nets are now USB_LINE_P/N. The 2026-10-26 manual revision also removes
D102 from both schematic and PCB, joining USB CC1/CC2 directly to HUSB320.
C115's leftover clamp bypass is removed in the 2026-10-27 reset; C116 is
also removed on 2026-10-31. This supersedes the earlier retained-CC-clamp
checkpoint; the routing plan preserves the current manual circuit.
Use XUNPU TS-1088-AR02016 / C720477, for RESET and the
two application controls. The manufacturer drawing gives a 3.9 × 3.0mm body,
2.0mm height, 160gf nominal force (±50gf) and 0.2mm nominal travel (±0.1mm).
Its two recommended lands are 1.05 × 2.0mm, with 5.5mm total outside span.
JLC's official component API returned componentLibraryType: base on 2026-10-25;
recheck at ordering. Two terminals are reasonable on the rigid PCB when pressed
vertically; protect the actuator from sideways snagging/lever loads and avoid
placing it on a flexing cantilever. This is an engineering judgement, not a
physical durability or tactile-feel result. SW101–SW103 retain the two-pin
Switch:SW_Push symbol and use the shared
Footprints:SW_SPST_TS-1088-xR020 footprint, pinned from KiCad 10.0.7 and
checked against the manufacturer drawing in the
library audit.
Drawing: XUNPU TS-1088 family.
Ear-current monitors and scaling¶
The selected IC is TI INA232AIDDFR / C5447660, DDF eight-pin thin SOT-23, with 2.9 × 1.6mm nominal body and approximately 2.8mm lead span. The selected two-terminal shunt is Milliohm HoYH0603-1/2W-10mR-1%-TCR50 / C2912774: 10mΩ, ±1%, 500mW, ±50ppm/°C, nominal body 1.7 × 0.9 × 0.65mm (0603). The manufacturer's HoYH electrical table explicitly gives ±50ppm/°C for 10–75mΩ in this size; the lower 2–9mΩ range has a different TCR. Use the manufacturer's shunt land pattern, not an assumed generic 0603 fit. JLC lists both selected parts for Economic/Standard PCBA; stock, price, exact footprint/paste and supplier-final assembly acceptance remain order-time checks.
Placement and connections¶
- U106/U203 are INA232A, with R132/R202 as their respective 10mΩ shunts.
Route
5V_L → shunt → EAR_5V_Land5V_R → shunt → EAR_5V_R. The full load current flows through the resistor, not through the INA232 package. - IC pin map: 1 IN+, 2 IN−, 3 GND, 4 VS, 5 SCL, 6 SDA, 7 A0, 8 ALERT. Check the TI DDF drawing against the actual library symbol/footprint before promotion; do not reuse the INA701 WCSP pin or land map.
- Use separate Kelvin sense pickoffs directly at each shunt pad: IN+ upstream, IN− at the ear/load side. Keep the short paired sense routes away from buck LX/clock aggressors and exclude load-current trace/via drops from the sense loop. Use deliberate wide current copper and review its short pad entries.
- Supply VS from local
3V3_L/3V3_R, GND from localGND_L/GND_R, with a local 100nF bypass. The IC accepts 1.7–5.5V supply, 3.3V I2C and −0.3 to 48V bus common mode, so 5V/12V load sensing is supported independently of VS. This headband remains a 5V USB design; this does not select 12V operation. - Both monitors remain on I2C1 and are polled; ALERT stays unconnected. With the selected A variant, left A0→GND_L gives 0x40, right A0→VS/3V3_R gives 0x41. The old INA701 0x54/0x55 addresses do not apply. Keep right logic/LDO consumption upstream of the right shunt.
Range and firmware scaling¶
Use the lower shunt-voltage range, ADCRANGE=1, configuration register
0x00 bit 12 (0x1000). Preserve reserved bits and select conversion times,
averaging and operating mode separately; a range-bit value is not a complete
configuration word. The following uses nominal R_SHUNT=0.010 Ω:
| Quantity / register | Selected scale or value |
|---|---|
| Shunt ADC range | Nominal ±20.48mV, corresponding to ±2.048A |
Shunt voltage 0x01 |
Signed 16-bit two's complement, 625nV/count |
| Current from raw shunt | I_A = int16(SHUNT_RAW) × 0.0000625 |
Selected CURRENT_LSB |
62.5µA/count, matching the raw shunt current step |
Calibration 0x05 (SHUNT_CAL) |
2048 = 0x0800 |
Current 0x04 |
Signed 16-bit two's complement; I_A = int16(CURRENT_RAW) × 0.0000625 |
Bus voltage 0x02 |
Unsigned bus field, 1.6mV/count, measured at IN− |
Power 0x03 |
Unsigned 16-bit; P_W = uint16(POWER_RAW) × 0.002 (2mW/count) |
TI's calibration equation includes the low-range divide-by-four:
SHUNT_CAL = 0.00512 / (CURRENT_LSB × R_SHUNT) / 4
= 0.00512 / (0.0000625 × 0.010) / 4 = 2048
POWER_LSB = 32 × CURRENT_LSB = 0.002 W
Write/reload SHUNT_CAL after power-up or reset: it defaults to zero, which
does not produce valid calculated current/power readings. Read/write 16-bit
register words MSB first. Signed full-scale current codes correspond to
−2.048A through +2.0479375A; the nominal ±2.048A range comfortably covers the
requested roughly 1.5A measurement headroom. The count size is quantisation,
not guaranteed noise-free resolution or accuracy. Firmware must use the new
addresses, register map and calibration; these notes do not implement a driver
or establish current firmware support. No firmware source was changed or
rechecked for this selection.
Current-path target and qualification¶
Target 1.25A continuous per complete ear supply/return path, allowing margin over 69 × 3 × 5mA = 1.035A plus sensing. At 1.25A the shunt drops 12.5mV and dissipates 15.625mW; at 1.5A it drops 15mV and dissipates 22.5mW. Neither the shunt's 500mW rating nor the monitor's ±2.048A range certifies the rest of the path or supplies overcurrent protection. Recheck headband and flex copper, pad/via necks, both connector ends, FFC and the joined-test links; the shared USB/upstream path must also cover both ears plus band loads. The ear connector's three supply and three return contacts would each carry about 417mA at 1.25A with equal sharing; verify the exact connector/cable rating, derating, sharing, voltage drop and temperature rather than assuming three parallel contacts establish capacity. Historical 750mA checks do not qualify this new target, and frozen manufacturing inputs are unchanged.
The FH34 series specification rates 0.5A/contact; its catalogue requires 70% of that rating when all contacts carry current. This design has six power contacts out of ten; the catalogue does not directly qualify that loading pattern at 417mA/contact. Keep actual cable/contact-sharing and worn temperature tests open. The Molex 781710002 socket is rated 1.5A/contact. The selected Molex 369200201 jumper is 100mm, 28AWG UL1571 and also rated 1.5A/contact. The provisional ear cable is GCT 05-10-D-0101-A-4-06-4-T, or equivalent pending selection. GCT's FFC ordering specification (B7, 12 June 2025) defines 101mm length, opposite-side contacts, 0.035 × 0.30mm conductors, 0.30 ±0.03mm supported ends and 0.5A/conductor for this construction. Using nominal copper resistivity at 20°C, the three-parallel-conductor supply and return have approximately 0.111Ω loop resistance: 0.138V / 0.173W at 1.25A, excluding both connectors. This estimate does not include tolerance, plating, bends or temperature. Cable choice may change to a lower-resistance Molex equivalent; retain the connector/mapping and loaded-fit checks. The 100mm power jumper's installed reach also needs checking against the actual band route.
The INA232's specified ±50µV input offset at 25°C, VS=3.3V and VCM=12V corresponds to ±5mA with 10mΩ; shunt ±1% tolerance, IC gain error, noise, temperature and supply/common-mode effects contribute separately. A 30°C shunt temperature change allows ±0.15% resistance drift at 50ppm/°C. Retain the source-dependent operating budgets and fail-safe policy below; the path target is not a default firmware current allowance.
Sources checked 2026-10-27: TI INA232 datasheet, pin table 5-1, address table 7-1, register tables and §8.1.1–8.1.2; INA232 JLC identity; Milliohm HoYH datasheet, pp.3–5; shunt JLC identity. The selected circuit and layout are applied: standalone/parent ERC and saved PCB DRC/parity are clear, and package/paste checks are recorded in the cleanup record. Loaded bench and supplier qualification remain pending.
Reversible microphone flexes and contact audio¶
Ordinary bottom-port PDM microphones stay on the headband. Use the same short, straight detachable mic-flex assembly on both sides, with local decoupling, open acoustic paths and opposite main-board L/R pulls. Select Gettop MD-DRA371-H10 / C50275760 on nominal 3.3V, matching the existing prototype. The common mic-flex source implements 40mm overall length, a 3mm neck with rounded end transitions, a 5 × 7mm mic island, standard 0.11mm yellow PI / 12µm copper per side, and 0.225mm rear PI at the tongue and mic. The rear support/adhesive has a Ø2.4mm acoustic opening around the Ø0.8mm PCB hole. Supplier mating thickness/tongue width, mounted acoustic seal/support and installed bending remain open; do not carry the standalone breakout's local SEL strap into this assembly. Use a 100kΩ SEL pull to local GND on the left and local 3.3V on the right. Gettop SEL=0 drives after the falling clock edge and SEL=1 after the rising edge; the other half cycle is high impedance. Verify receiver channel identity and shared-data timing on the assembled cable. Put 100nF at each mic, leave DATA without pulls, and use separate 100Ω 0402 R117/R118 on the left/right CLK branches, near the GPIO9 source. These reuse Basic C25076 and provide an initial damping value within Gettop's 50–100Ω recommendation for long clock connections. Check clock edge rates at both microphones with the real cable.
Reuse FH34SRJ-10S-0.5SH with this reversal-symmetric logical map:
3V3, GND, DATA, CLK, SEL, SEL, CLK, DATA, GND, 3V3
Join paired contacts to their nets on both main and mic flex. The symmetry preserves signals/channel selection under reversal but does not prove physical pin-1/contact-face continuity. Verify both insertion orientations, body/port clearance, actuator access, retention, 5.5mm tongue width and 0.30 ± 0.03mm mating thickness against the exact connector drawing. Mark MIC / EAR / BAND sockets distinctly: the common connector part does not make these interfaces electrically interchangeable.
Preserve full BX contact-audio capture alongside stereo PDM, even though the experiment is VAD rather than high-fidelity audio. Reserve TDM and required IRQs as well as I2C/motion access. The initial BX format is 16kHz WCLK, 2.048MHz BCLK, eight 16-bit TDM slots, with Z/Y/X in slots 0/1/2; configure the receiver's framing/edge alignment to match the BX. Other slots are high impedance. PDM can initially use 16kHz PCM at 128× oversampling (2.048MHz CLK), subject to the IDF receiver configuration. I2S0 and I2S1 have separate clocks; the shared nominal rate does not establish synchronisation. Buffering, timestamps and capture latency remain firmware/bench work. Mounted tests must distinguish own speech from ambient speech, head motion, band/fur rubbing, button presses and USB-cable handling, while checking comfort and sensor stress.
BX timing specifies ±0.1% clock frequency and 4ns peak-to-peak BCLK jitter. The S3's fractional I2S clock divider needs waveform qualification against that limit; a nominal 2.048MHz setting alone does not prove compliance. Retain clock test access and treat this as an experimental contact-audio bring-up gate.
Cross-band cable¶
Use the manually added Molex Pico-EZmate 78171-0002 / C505023 sockets J105/J205 and the Molex 369200201 preassembled power jumper, plus the separate ten-position FH34SRJ signal link, with the local right-side LDO. Carry right-ear current plus right-board load and budget outgoing/return drop, connector resistance and temperature. Provide cable retention and strain relief. The selected power jumper connects 1→2 and 2→1: J105.1=GND_L / .2=5V_L; J205.1=5V_R / .2=GND_R. Both sockets' mechanical pads use local GND.
| Left band FFC contact | Function |
|---|---|
| 1 | GND |
| 2 | I2C1 SCL |
| 3 | I2C1 SDA |
| 4 | GND |
| 5 | Right PDM CLK |
| 6 | Right PDM DATA, joined to the left mic DATA at the controller |
| 7 | Right outer LED data |
| 8 | Right inner LED data |
| 9 | GND |
| 10 | GND |
There are six signal nets and four ground contacts. BX audio is local to the left main; microphone SEL stays local to each main/mic pair. No cross-band 3.3V rail is needed with the right LDO. The wire pair does not replace each ear FFC's three power and three GND contacts. Signal-flex grounds remain parallel current return paths; check sharing, ground shift and PDM/I2C behaviour with the real cable.
The selected cross-band FFC reverses numbering, J104.1→J204.10, etc. The right socket's map is the reverse of the left table, using the distinct right nets after the temporary links. Both main boards are oriented as installed. Verify actual contact-face continuity and strain relief with the selected cable. Eight temporary joined-board paths carry six signals plus 5V/GND; every path must be isolated after separation. Use distinct left/right net names around the cut-links so exported connectivity can prove that separation removes the temporary connections. The signal cable and wire pair then supply the connections. No extra analogue touch or GPIO14 shield conductor is reserved.
I2C buses and addresses¶
All addresses below are 7-bit, without the read/write bit. I2C0 uses GPIO16 SDA / GPIO15 SCL; I2C1 uses GPIO10 SDA / GPIO11 SCL. R107 pulls I2C0 SCL up and R108 pulls I2C0 SDA up. The ear buses extend these same two buses; no bus multiplexer is planned. The INA232 rows describe the applied schematic/PCB replacement. The former INA701 addresses 0x54/0x55 are historical; firmware still needs the new device protocol, addresses and calibration.
| Bus | Device / location | 7-bit address | Address selection |
|---|---|---|---|
| I2C0 | U102 HUSB320-BA000-QN12R, left main | 0x42 |
ADDR to GND through R123, 200kΩ |
| I2C0 | U104 LSM6DSV16BX, left main | 0x6A |
SA0 pulled to GND through R131, 10kΩ |
| I2C0 | U105 LTR-F216A ALS, left main | 0x53 |
Fixed address |
| I2C0 | Left ear U1, AW96105 | 0x12 |
Default address with CS2 floating; selected master part |
| I2C1 | U106 INA232A, left ear-feed monitor on left main | 0x40 |
A0 connected to local GND_L |
| I2C1 | U203 INA232A, right ear-feed monitor on right main | 0x41 |
A0 connected to local VS / 3V3_R |
| I2C1 | U202 LTR-F216A ALS, right main | 0x53 |
Fixed address |
| I2C1 | Right ear U1, AW96105 | 0x12 |
Default address; generated from the selected left master |
There are no address collisions within either bus. Both ear sensors can retain
0x12, and both ALS devices can retain 0x53, because each pair is split across
the controllers. Both INA232s share I2C1, including the physically left-hand
monitor, so their different A0 straps are required.
The AW93205 manufacturer specification
confirms default 0x12; the
AW96105 datasheet
(June 2020 V1.0, pp.2/14) specifies 0x12 with CS2 floating. Either candidate
therefore uses the bus/address allocated to that ear.
For already implemented devices, band address selections were checked against
the saved nets and the
HUSB320 ADDR table,
ST I2C interface specification,
Lite-On I2C address
and, for the fitted monitors,
TI INA232 Table 7-1.
The saved band sockets have J102.6/7 carrying I2C0 SCL/SDA and J202.6/7
carrying I2C1 SCL/SDA, using the _R nets after the cross-band link. This
matches the ear's 6=SCL / 7=SDA assignment; the swap is already applied.
The saved build/headband-wroom-apply-20261030/design.xml netlist records
these four pin/net assignments. The current intended ear
cable is 1→1, with the connectors the same way up and one 90° fold to allow
ear-position adjustment. This is a planning assumption pending actual conductor
continuity; the fold alone is not electrical evidence. Preserve the revised
J102/J202 poses and their existing rail/LED order. Cross-band numbering still
reverses: J104.2/3 connect to J204.9/8 for I2C1 SCL/SDA. Both band ear
connectors put inner LED data on contact 5, matching the current ear master.
Use one 4.7kΩ pull-up pair per bus on the left main: R107/R108 for I2C0 and R109/R110 for I2C1. Verify resistance against total cable/device capacitance and rise/sink limits. 100kHz is an initial bring-up target. Verify sequencing/backfeeding and keep each ear regulator output isolated.
Controllers and resource allocation¶
| Function | Resource requirement |
|---|---|
| Stereo PDM | I2S0 PDM RX, shared CLK/DATA; explicitly compatible microphone timing |
| BX contact audio | I2S1 TDM RX BCLK/WCLK/data, I2C0 control and required IRQs |
| Four LED chains | Four RMT outputs/GPIOs; verify memory/channel allocation and concurrent workload |
| Native USB Serial/JTAG | Socket D−/D+ to GPIO19/GPIO20 with routing/protection; HUSB320 handles CC separately |
| Application controls | Two GPIO buttons; separate RESET on EN/CHIP_PU, open GPIO0/GND BOOT jumper |
Use 100Ω source series resistors on the four LED outputs. External LED DIN pulldowns R132/R133/R202/R203 are removed by prototype choice: rely on LED input bias and send a blank frame shortly after power-up, as Andi intends. Keep that startup policy in the firmware handoff; this hardware change does not establish four-output firmware support or verify the physical power-on waveform.
The 31 October firmware source recheck
finds the v2 four-chain map and one 48-symbol S3 RMT memory block per chain
in components/leds/ear_rmt.c. Legacy two-output profiles retain two blocks
per ear; the 25 October audit describes that earlier implementation.
Qualify refill timing and concurrent PDM/TDM capture under radio and flash load
on the mounted hardware. Source inspection does not establish runtime acceptance;
the IDF RMT resource guide
does not establish four-chain runtime acceptance.
The currently saved schematic allocation for ESP32-S3-WROOM-1-N16R8
follows the 2026-10-30 migration.
The former MINI module cannot provide the PSRAM required by the intended voice
processing. Directions are relative to the MCU; application logic is nominal 3.3V.
Firmware has not been changed by this hardware task. The 31 October manual-layout
completion swaps the two right LED outputs to GPIO6 outer / GPIO7 inner; firmware
board.h still had GPIO7 outer / GPIO6 inner at the recorded read-only check.
| GPIO | WROOM module pad | Function | Direction / external bias |
|---|---|---|---|
| 0 | 27 | BOOT rear jumper | Input; pull-up, ground for ROM recovery |
| 16 / 15 | 9 / 8 | I2C0 SDA / SCL | Open drain; 4.7kΩ pull-ups |
| 10 / 11 | 18 / 19 | I2C1 SDA / SCL | Open drain; 4.7kΩ pull-ups |
| 5 / 4 | 5 / 4 | Left outer / inner LED data | Outputs |
| 6 / 7 | 6 / 7 | Right outer / inner LED data | Outputs through band link; 31 October routing swap |
| 9 | 17 | PDM CLK | I2S0 output; separate series resistors per branch |
| 8 | 12 | Shared PDM DATA | I2S0 input; no pull-up/down |
| 13 / 14 / 21 | 21 / 22 / 23 | BX BCLK / WCLK / DATA | I2S1 outputs / output / input |
| 38 / 39 | 31 / 32 | BX INT1 / INT2 | Inputs; configure BX output mode in firmware |
| 12 | 20 | HUSB320 INT_N | Input; open-drain pull-up |
| 19 / 20 | 13 / 14 | USB D− / D+ | Native USB Serial/JTAG |
| 41 / 42 | 34 / 35 | Application buttons 1 / 2 | Active-low inputs |
| 43 / 44 | 37 / 36 | Rear UART0 TX / RX test pads | Output / input |
| EN | 3 | RESET | Separate active-low button and EN RC network |
Leave GPIO3/45/46 strapping pins unused for application functions. GPIO1/2/17/18/40 remain unallocated. Pads 28–30 / GPIO35–37 are unconnected for the N16R8 module's octal PSRAM. GPIO47/48 (pads 24/25) are also unconnected, preserving the option of WROOM-2, where these are 1.8V-domain signals. GPIO26 is no longer an application signal. These restrictions follow the WROOM-1 datasheet and WROOM-2 datasheet.
The shared custom symbol preserves existing schematic wire endpoints while
renumbering the physical module pads. The fitted footprint is
Footprints:ESP32-S3-WROOM-1_BandOverhang: stock WROOM-1 copper, underside ground,
drills and paste, with off-board silkscreen trimmed. The overlapping WROOM-2
ground provision is removed by design choice on 2026-10-31. See the
library audit.
Unused GPIO47/48 remain available for future flexibility, but the current PCB
land/paste pattern does not claim WROOM-2 compatibility.
Viewed from the component side, the module at (128.75,127.75), 270°, has its antenna beyond the x=135 PCB edge. USB pads 13/14 are at (118.77/117.50,119.00); BX clock/data pads 21/22/23 are on the left edge, y=128.385/129.655/130.925. The GPIO41/42 button pads and UART pads lie along the lower edge. RESET retains EN pad3. The new routes are pending; the former MINI routing acceptance does not apply to this placement checkpoint.
Native USB supports programming/debug and automatic download entry. Preserve manual GPIO0-low plus RESET recovery via the rear jumper. No ESP-PROG header is fitted; only the rear UART TX/RX probe pads remain. ALS interrupts and INA232 ALERT pins are unused; poll them. GPIO39/41/42 have alternate external JTAG functions, but this board uses native USB Serial/JTAG and assigns those pins to BX/buttons. Firmware integration remains separately authorised work.
Check the final connector orientations, pin escape, USB pair, clock return paths, ground continuity and RF/buck separation during actual placement/routing. The concept review does not establish routed lengths or signal integrity.
Draw local circuits with wires and real power symbols, using the symbols' Value
fields for 3V3_L/R, 5V_L/R, EAR_5V_L/R and GND_L/R as
appropriate. KiCad 10 derives the power-net name from that field; a disposable
netlist trial confirmed repeated left ports connect while left/right rails remain
distinct. Use ordinary labels at meaningful block/sheet boundaries, not on every
passive terminal. See the KiCad power-symbol documentation.
USB, power and startup policy¶
Use HUSB320-BA000-QN12R for Type-C CC/current advertisements, with PORT and ADDR each 200kΩ to GND (R122/R123, C25764; sink, address 0x42), EN_N grounded, VDD at 3.3V and VBUS_DET connected for this exact variant. BA001 has a different VBUS_DET resistor requirement and is not an automatic substitution. No assumed USB-PD negotiation or elevated VBUS; verify detach, advertisement changes and missing/stale status.
The 2026-10-29 strap selection replaces the datasheet's 900kΩ recommendation with a stocked Basic 200kΩ part. This deliberately accepts stronger pull-downs and potentially higher bias current for the USB-powered design; it is an engineering substitution, not a manufacturer-specified alternative resistance.
Keep band rails named 5V_L, 3V3_L, GND_L and 5V_R, 3V3_R, GND_R:
generic global ear +5V/+3V3/GND must not bypass an ear shunt or parallel local
regulators in the parent schematic. Cable connections remain separate assemblies;
verify band standalone and parent-context netlists.
- Reserve MCU/RF, microphones, monitors, ALS, regulators and LED idle draw before assigning ear budgets. Per-ear INA readings do not measure whole-device load.
- With no higher advertisement, ~100–150mA per ear is a target ceiling, reduced further or held black if default/unenumerated USB constraints require it.
- With 1.5A/3A advertisements, raise configured limits only within the available input, cable, thermal and per-ear margins. The earlier ~500mA-per-ear operating target may be raised toward the roughly 1A load only when the source budget and qualified path permit it. The new 1.25A path target is not a default allowance or an already established capacity.
- Allow an explicit known-source override, with persistence/detach/reset semantics still to define. Start black, establish safe budgets, then normally enable animation. Recovery+test defaults off and diagnostics obey the same limits.
- Enforce the 70% blue ceiling across saved/user settings, overrides and output rounding. Define safe CC/monitor fault fallback and source-downgrade behaviour.
- Characterise clocked black/channel currents, inrush, rail transients, cable/ connector drop, regulator stability and worn temperatures with bench input measurements plus both INA232s after replacement. Firmware limits are not short-circuit protection.
Firmware interface deliverables¶
The hardware/firmware handoff is a dated software snapshot. Inspect current firmware read-only before making support or cadence claims; old 47/50-pixel scheduling limits do not constrain this layout. This repository does not authorise firmware edits, builds or tests there.
Return these contracts for a separately authorised firmware task:
- Module pad/GPIO/net, direction/voltage/pulls, connector contact, peripheral, address and required IRQ/alert for every fitted device and later population.
- A per-pixel map with refdes, chain/DIN and logical indexes, L/R identity, coordinates, edge/region, height/arc position and explicit reversal. Define curved-base/inner participation and complete physical-chain clearing plus saved-count migration without losing unrelated settings.
- BX motion/contact-audio roles, mounting axes/calibration identity, rates, timestamps/freshness and fault policy; PDM/TDM format and simultaneous capture.
- USB/current/startup/blue-cap policy, monitor units/freshness and fail-safe behaviour, controls and normal/recovery image identity. A reserved recovery partition is not an implemented recovery+test image; changed partition tables/ bootloaders need a deliberate install plan, with NVS preserved.
- Concurrent LED/PDM/BX/USB/radio/sensor/flash and OTA-health validation, including deadlines, capture loss, buffer/heap/stack budgets and degraded startup.
Separate microphone prototype¶
The MD-DRA371-H10 breakout is a separate 14 × 16mm rigid PDM microphone prototype. Its five-board order inputs are frozen here. Supplier-final placement files and physical/acoustic acceptance remain pending; the headband now selects the same microphone, while its reversible flex construction remains separate design work. Preserve the prototype and its order record during main-project work.
Vendor references¶
JLC flex capabilities, FPC clearances, panel guide, stiffeners, rigid stack selection, S3 module positioning, I2S, USB Serial/JTAG, BX datasheet, MEMS mounting, INA232, FH34SRJ product/drawing, LTR-F216A datasheet, IQS231AB and Azoteq application notes.
These links are retained from the design review; this documentation edit does not refresh supplier rules or validate hardware. Recheck official sources at design/order time.
The previous full root plan is retained at git show 1eacca2:PLAN.md. Current
manufacturing constraints and build/checkpoint evidence belong in the
quote pipeline, flex rules and
archive.