Two-set headband panel for Standard PCBA¶
2026-11-01: WROOM-1-N16R8 carrier. The 35 × 73.5mm joined source includes the manual routing, supply-via cleanup and denser internal L/R bridge perforations (24 aligned holes per set, including border-centred end holes) and R0.5 rounded-rectangle slot. The outer carrier tabs are unchanged. The source USB model reference is also repaired. Earlier MINI packages are historical and must not be uploaded for this design.
Latest revision, 1 November: the R0.5 slot is now 8.5mm long, with its ends
aligned to the adjacent drill edges. The subsequent manual-routing review and
local DRC/reference fixes are recorded in the layout log.
The subsequent silkscreen pass adds white ink, connector polarity/function labels
and bridge-link names without changing copper or placement.
The 2 November pass moves U references to the rear, adds front chip labels and
the neggles.dev logo, and reserves a 5mm rear QR replacement square per set.
The follow-up projects chip-body outlines onto the rear beside 0.8mm U references,
fills and centres the logo below espurr v2 band L, and places its domain directly
underneath. A two-line rear USB-C / 5V 3A legend identifies the supply input.
The 0.8mm minimum text-height rule now matches the selected lettering, so the
text-height warnings are gone. Only the four expected panel library warnings
remain. Rear branding and the QR target move clear of the continuous U101 outline;
U101 is between TX/RX and BOOT, with the board name centred above the outline.
The left title is centre/centre at the centre of its actual strip; all visible
right-main labels are rotated 180°. Printed labels retain that orientation through
panelisation, and verification compares the full 360° orientation after undoing
the panel-copy rotation, rather than treating 0° and 180° as equivalent.
Connector lettering is Title Case, with closer Band labels, compact matching
leaders, vertical Mic R text and smaller bridge legends. A/B arrows share the
device-label arrow style. These are silkscreen-only changes.
Mic L is also vertical (90° counterclockwise) to the left of its socket, and the
left INA label sits left of its chip; both use short horizontal pointers.
Mic R also reads at 90° following a text-only 180° flip, with its anchor/pointer held.
The subsequent front-label pass removes the redundant ESP32 label and pointer,
rotates USB CC 90° counterclockwise, and places it along the left board edge below
the similarly rotated Buck label, just above the CC resistors. Both labels use
0.8mm text with orthogonal, rounded pointers approaching each chip from above.
USB CC is nudged 0.5mm upward to clear its pointer stem. Copper and component placement
are unchanged. The cleared front area now carries the shared
Footprints:Logo_ESPurr_5mm mark, now at (111.5,118.25)mm after the 7 November
manual adjustment, with its native 0.8mm
espurr text below. LOGO102 is board-only, excluded from BOM/CPL, and has no pads
or copper. Existing rear branding is retained.
The complete 7 November regeneration includes the later manual routing and label
adjustments, including repositioned Buck, USB CC, IMU and Mic L annotations.
Use build/headband-manual-release-20261107/review.html for the board/panel gallery
and build/headband-manual-release-20261107/release/build/panel/ for uploads.
Panel revision e057f665, unit revision bab71f1b, source/tooling snapshot
5aeb758. Saved/refilled unit DRC/parity and standalone/parent ERC are clean;
all 143 repository tests pass. The panel retains only the four
intentional library warnings. All four copper layers match the transformed unit
within the established CAM tolerance. BOM files are byte-identical to the previous
package (66 fitted parts per set, 132 per panel); CPL changes only R130, moved
2mm upward, and its two panel instances. Use the new matching CPL.
The panel preparation disables keep-upright on footprint silk text in its
disposable copy, preserving the logo lettering through the second copy's 180°
rotation. Native checks cover all three artwork footprints and their text.
Supplier processed-file/placement review and physical acceptance remain open.
Run just band-panel build/headband-panel-YYYYMMDD with a fresh output directory.
The driver runs kikit panelize, using the checked-in
scripts/espurr_hw/data/headband-panel.json preset and KiKit tab annotations.
A small CentreBridge hook adds the central stopping line that KiKit's
bounding-box partitioner cannot infer between the nested L shapes.
KiKit constructs the substrate, routed outline, frame, mousebites, tooling holes
and fiducials. Native KiCad preparation and independent verification operate
only on disposable copies. No source PCB, library, routing or component placement
is changed. KiKit 1.8.1 / KiCad 10.0.7 were used for the first panel.
Files and order settings¶
Upload the root espurr-band-panel-unit/ files: those describe one joined
assembly and are retained as electrical/geometry evidence.
The design-input hash and exact filenames are recorded in manifest.json under
downloads. The matching -Production.zip contains all three upload files;
extract that bundle first. See the hash convention.
The panel revision additionally hashes the KiKit preset and the native preparation/centre-bridge
recipe files, which contain tab locations and other carrier geometry. Exporter
timestamps and output folders cannot change the revision.
Printed component references retain their unit names (for example U104).
The panel BOM/CPL still uses unique B0_/B1_ prefixes. On the disposable panel
input only, visible reference fields become identical fixed silk text before
KiKit renames the assembly references; transformed text positions, sizes, layers
and orientations are verified along with the copper.
QR marking¶
Official JLCPCB marking instructions, checked 2026-11-02, require a solid silkscreen square matching the selected code size. Select 2D barcode only → QR code → 5 × 5mm → Specify Position, rear side. The panel has one B.Silkscreen square on the left main of each headband set, two targets total. Leave the carrier attached; neither target is on scrap. Request one serial marking per headband set and confirm how JLC assigns numbers across the two panel copies; this is not established by the CAD checks. Enable Confirm Production File and inspect the supplier's qrb layer for both locations, the 5mm size and replacement of the solid squares. Prefix/start number choices belong to the order, not to this PCB artwork. The local raytraces show the solid placeholders, not the supplier-generated QR codes.
Board and assembly settings¶
- Panel by customer, 75 × 91.5mm, two identical complete headband sets. Each set contains its original joined left/right boards and electrical test bridge.
- Standard PCBA, top-side assembly; Standard remains the target because the earlier quote required it for the LSM6DSV16BX. Recheck the WROOM selection and stock in the portal. One panel has 132 fitted placements. Two assembled panels therefore produce four headband sets; check the portal's quantity interpretation before payment.
- Four-layer rigid FR-4, nominal 1.6mm, standard JLC04161H-7628, outer 1oz / inner 0.5oz copper, ENIG, green mask and white silk on both faces.
- Customer-supplied frame: 6mm top/bottom rails with 3mm board gaps, 5mm side rails with 2.25mm board gaps, and three 2mm NPTH tooling holes. Three global fiducial locations (1mm copper / 2mm mask opening) on each face. Fiducial centres remain 3.85mm from the outer edge; their 2mm mask openings now have 1.15mm to the inner top/bottom rail edge. Do not add another set of rails. KiKit expands the nominal 5mm frame vertically to meet the 91.5mm minimum height.
- Mousebite separation, no V-cuts. Six 4mm-wide carrier tabs per assembly, twelve around the frame, plus one 4 × 13.5mm central bridge connecting the two main boards. The central bridge has a mousebite row at each end: fourteen rows total, five 0.6mm NPTH holes per row with nominal 0.9mm spacing. Hole centres are offset 0.3mm toward the disposable carrier so existing board copper is preserved; remove/deburr remaining nubs. Global KiKit milling fillets are disabled so they cannot round the existing board/joint geometry.
- Leave the outer carrier and each internal electrical bridge attached for shipping. Remove the carrier with the board supported, cutting tabs rather than bending the IMU corner. Keep each internal bridge until assembly testing is complete.
The stepped source outline is nested by alternating 180° rotation with a negative grid spacing. The source package envelopes leave 3.4mm between the closest body and the neighbouring PCB, including antenna overhangs. The original left/right mousebite fixture and its power/signal links are retained. Tabs avoid the BX corner, USB socket and module antenna. The central bridge added on 2026-10-30 joins the facing main-board edges clear of both antenna bodies; remove it during depanelisation along with the outer carrier.
Manufacturing-copy RF handling¶
U101's library courtyard includes a large RF clearance envelope, and its footprint-owned antenna keepout lies wholly outside the source PCB. A neighbouring board temporarily occupies that free-air region in the nested panel. Leaving the keepout intact would erase the neighbouring copy's pours when KiCad refills.
The input-copy preparation verifies that the antenna keepout does not intersect the finished board, removes that one off-board keepout from the manufacturing copy, and replaces U101's oversized RF courtyard with its F.Fab body envelope plus 0.25mm. The saved source and shared library retain the complete RF keepout. Other keepouts, including connector restrictions, are preserved. This is not a waiver for copper on the finished board. Perform RF qualification after separation, not while another board/carrier occupies the antenna's free space.
The four library mismatch warnings are deliberate panel-copy differences: two U101 instances have the keepout/courtyard edits above, and KiKit moves each MB101 slot's eight Edge.Cuts primitives from the footprint into the panel board outline. Their 24 drill pads and two rule areas remain. The source unit matches its libraries. These warnings remain explicitly accepted; no generated library variants or broader DRC suppression are added to hide them.
Small manufacturing-copy pour-only keepouts at each new tab retain the original
0.3mm copper-edge clearance. This prevents refill from growing copper into the
carrier tabs while preserving the original pour outlines and corner smoothing.
The source pour shapes remain unchanged. Unit and panel refill both use 1µm curve
approximation (recorded in each fill.json) rather than the saved 5µm setting;
this avoids a narrow-connection artefact seen on the rotated right ground pour.
Using the same accuracy prevents mismatched thermal/sliver copper in comparison.
The saved design rules remain unchanged. CLI DRC checks those freshly filled
polygons without refilling them again. All four exported copper layers still
have to match the transformed source within the documented 11µm tolerance.
Assembly data and verification¶
Panel references are B0_<original> and B1_<original>; the second copy is
rotated 180°. The BOM contains both copies and exactly matches the CPL's 132
references. Tooling holes, fiducials, copper jumpers and test pads are excluded
from the fitted population. Nets are independently prefixed for each copy.
Source JLCPCB_CORRECTION fields are applied after the copy's physical
rotation. U103, U106, U201 and U203 each retain their explicit 180° correction
on both copies. Coordinates are mm, referenced to the panel plot origin.
Inspect both copies in JLC's placement preview, especially polarized/IC packages
and asymmetric connectors, before ordering.
The workflow checks source-unit ERC, refilled DRC and schematic parity; panel DRC and opens; a connected, closed carrier outline; source-to-panel footprint, numbered-pad, net, trace and via transformations; tab/tooling/fiducial counts and the central bridge/its component clearances; body clearances; BOM/CPL parity; actual Gerber and drill inventory; and all four copper layers against the transformed source CAM, allowing only the added fiducials and an 11µm comparison tolerance (twice the source 5µm curve approximation limit plus 1µm CAM rounding). All source hashes are checked before and after generation, including on failure.
The source unit is free of DRC warnings. Four library-mismatch
warnings are expected: the two U101 assembly courtyards deliberately differ from
the RF library courtyard, and KiKit moves the two MB101 bridge footprints'
Edge.Cuts graphics into the panel outline. No electrical errors or opens
are accepted. manifest.json is written only after checks pass and has status
PANEL_QUOTE_FILES_GENERATED_PREVIEW_REQUIRED.
This is a quote package, not supplier or mounted-hardware acceptance. JLC must confirm the panel, breakaway features and placement preview; mechanical strength, current/thermal performance, RF and sensing operation remain hardware checks.
Official references checked 2026-10-31: KiKit CLI examples, JLC Standard assembly capabilities, rails and fiducials, process-edge/tooling dimensions, mousebite guidance.