JLCPCB flex rule profile¶
Rule checks were reviewed 2026-10-17 with KiCad 10.0.7. The requested ear flex and nominal CAD model are 0.12mm / 0.5oz copper per side; the ear-stack contract owns that selection and the 18µm nominal electrical model. Supplier limits below retain their dated review scope and still need order-specific confirmation.
The ear and parent placeholder retain the flex manufacturing constraints, via presets, mask defaults and custom rules. The headband now uses its separate rigid-board profile. Netclasses and placement restrictions remain project-specific. The ordered microphone breakout and its manufacturing record are frozen and excluded from this profile.
The authority is JLC's flex capability table and FPC clearance guide. Remaining hole constraints use the general capability table, as delegated by the flex table. Discrepancies are resolved conservatively here; they still need confirmation for the actual order.
Installed constraints¶
All dimensions are millimetres. These are limits, not preferred routing sizes.
| Check | Installed value / scope |
|---|---|
| Copper clearance, track width, connection width | 0.127; project margin over JLC's 0.1016 trace/space limit |
| Copper to laser outline / internal cutout | 0.30; requires correct closed Edge.Cuts geometry |
| Via copper to outline | 0.50; stricter FPC guide |
| Regular through via | Diameter ≥0.55, drill ≥0.30, annulus ≥0.125 |
| Other drilled pads | Drill 0.10–6.50; vias also have the 6.50 maximum |
| Plated component annulus | ≥0.18; JLC recommends 0.25 |
| Plated slot | Minor drill dimension ≥0.50 |
| Hole to unrelated copper | Global 0.25; plated component holes 0.28 |
| Hole to hole | Global 0.25; pairs involving drilled component pads 0.45 |
| Pad to unrelated track / arc | 0.20; conservative FPC guide value |
| Tagged BGA pad | Both dimensions ≥0.25; unrelated route gap 0.20 |
| Coverlay opening expansion | +0.10 per side |
| Coverlay web | 0.50; KiCad merges narrower webs in plotted openings |
| Opening to unrelated copper | 0.15 native mask clearance check |
| Via tenting | Both sides enabled; custom assertion rejects explicit untented overrides |
| Silk text | Height ≥1.00, stroke ≥0.15 |
| Unfilled silk graphics | Stroke ≥0.15 |
| Silk to coverlay opening | 0.15 on both mask layers |
Blind, buried and microvias are prohibited. The paid small-via exception is not enabled. Routing presets are 0.55/0.30, 0.60/0.30 and 0.80/0.40 diameter/drill; 0.60/0.30 provides additional annular margin. Existing generic netclasses can still propose smaller vias, which DRC rejects. Netclass dimensions are routing defaults, not fabrication waivers.
Minimum silk item clearance remains 0 to avoid imposing an arbitrary gap between pieces of one symbol. Native overlap checking and the separate 0.15 silk-to-opening rule still apply. Microvia dimensions are inactive because that via type is disallowed. The 0.10 global drill minimum does not permit 0.10 vias: the via-specific custom rule requires 0.30.
The same-footprint solder-mask bridge option is enabled to accommodate grouped coverlay windows. This changes which joins native DRC reports; it does not approve package fanouts or copper exposed inside a shared window. Per-pad and per-footprint overrides still require inspection.
Validation and use¶
Run just test-flex-rules after editing the profile. It creates native KiCad
geometry in build/flex-rules/tests/, checks twenty failing/passing case pairs
with the installed CLI, and repeats with custom rules removed. This exercises
via drill/diameter/annulus/edge/tenting, microvia rejection, plated holes/slots,
hole spacing, pad-route spacing, BGA size, silk text/graphics and both mask sides.
It checks actual diagnostic rule names and item UUIDs. Source hashes must remain
unchanged. A CLI exit code alone is insufficient: KiCad can run DRC after a
custom-rule compilation failure.
KiCad 10 uses the enum A.Fill == 'None'; the manual's boolean Filled is stale.
The mask clearance rule uses (layer "?.Mask"): B.existsOnLayer(...) did not
match the combined mask geometry in the regression fixture. Rules sharing a
condition are combined. Keep general pad-drill rules separate from via-drill
rules so their precedence cannot reduce the regular-via minimum.
The silk-to-mask clearance fixture uses footprint artwork. Native combined-mask checking can skip standalone board graphic-to-mask pairs; inspect exported ink against coverlay as part of CAM review. Text/stroke assertions alone do not establish printable feature widths inside arbitrary filled artwork.
Custom constraints can override ordinary settings, so retain meaningful global floors and review future exceptions. Physical pad-route clearance adds a check without replacing a stricter electrical netclass clearance. BGA checks require the pads' native BGA fabrication property; package names are not inferred.
Run just ear-coverlay-check on the saved ear to export the actual merged mask
Gerbers on a staged copy. It checks both-side via tenting, copper-land coverage
and a 0.30mm drilled-hole-edge-to-opening gap, including same-net openings.
Copper-ring clearance is reported separately. This is the project's interpretation
of the JLC illustration, not supplier CAM approval. A tented via can still
be exposed by a nearby pad or merged window. Results and the inspected source
hashes are written to build/flex-rules/coverlay/. This is a narrow check;
ordinary DRC and the remaining CAM review are also required.
The retired ear-flex-check was tied to the data planner's two-touch-zone
geometry and refused additional pours/rule areas. That refusal was not a clean
flex result. Its factory-CAM companion retained the earlier 50-LED population
contract; see the retirement record.
Use the current quote pipeline, just aw-ear-fab and
just test-aw-ear-fab for the AW-equipped design. Any port of the historical
checkers is separate tooling work.
Stackup and remaining gates¶
The saved ear and empty parent placeholder use 0.120mm nominal total, with 18µm copper per side, 25µm PI and 29.5µm nominal white coverlay/adhesive per side, black silk and ENIG. This is a CAD envelope; actual white coverlay may make the finished flex thicker. Electrical estimates use 18µm nominal copper, with supplier construction/tolerance still open. The parent PCB remains an empty hierarchy placeholder. See the stack update for saved readback and checks.
KiCad constraints do not establish bend life, minimum feature size of arbitrary filled artwork, stiffener material/extent, component-to-bend clearance, panel handling, cable construction, assembly eligibility or actual white-coverlay registration. Keep those as documented CAM/mechanical/assembly gates. Review large coverlay windows and intentionally exposed package fanouts. Laser-routed cutouts must appear in Edge.Cuts; drawing-layer slots receive no copper-edge check. A slot represented as a drilled NPTH pad receives the ordinary hole clearance check, so verify its applicable routing clearance separately. No layout geometry was repaired by installing this profile.