Headband library acceptance¶
Pin-map review dated 2026-10-25, for the first schematic. This is library/electrical identity acceptance, not a routed-board or supplier release. Sources are manufacturer documents; cached PDFs, parsed readback and disposable renders are under build/headband-schematic-2026-10-25/.
Custom symbols were created individually through Konnect in the project-global ../symbols.kicad_sym, under the existing Symbols: alias. New footprints are in ../footprints.pretty, under Footprints:. Existing entries, library registrations, ear source and hand-fixed assets are preserved; unused temporary band-local libraries were removed. Existing standard IDs are retained when they match the package. Standard KiCad library assets retain KiCad's CC-BY-SA-4.0 plus library exception; new symbols/footprints are hand-authored from manufacturer package data, with no EasyEDA or other third-party ECAD geometry import. Manufacturer documents/models retain their original rights; no new 3D models are supplied for the new footprints.
The acceptance procedure queried every library symbol and pad set, placed disposable schematic/PCB instances, rendered them, and independently read PCB pads with native KiCad 10 pcbnew. Konnect's saved-board pad reader returned Footprint not found for a visible scratch instance; native readback plus direct KiCad plots are the independent evidence. No source PCB was touched. Schematic symbols were inspected in library-acceptance/symbols.png; physical pads/numbers in footprints-final.kicad_pcb, physical-readback.json and numbered Fab plots. Physical coordinates below are the final footprint-local top/component view, with X right and Y down. Symbol coordinates use library X right/Y up. Every row joins the manufacturer's physical lead to the symbol and footprint; mechanical/duplicate features are listed explicitly.
Branding and QR artwork — 2026-11-02¶
Footprints:Logo_neggles_dev_7.5mm copies the embedded neggle-logo-0.12
artwork from neggles/esp-pmsa, commit
f5bde7ff7e79f871161c57362535a3440508316b, esp-pmsa/esp-pmsa.kicad_pcb, LOGO1.
Author: neggles / Andromeda Holmes; that project's LICENSE.md is CC-BY-SA 4.0.
Reuse here was explicitly requested by the author. The original 45 native Bezier
curves and 0.127mm line widths are preserved, without rasterisation or scaling.
Reference/value fields are hidden, foreign schematic linkage is omitted, and
the new library ID/description and PCB-only/BOM/placement exclusions are added.
The footprint is front-normal in the library; KiCad flips the placed instance
to the rear. The separate neggles.dev text is board artwork.
The fitted Footprints:Logo_neggles_dev_7.5mm_Filled is a filled derivative,
also CC-BY-SA 4.0, created at the author's request. The two closed contours are
sampled at 128 intervals per cubic, filled with the central diamond aperture
preserved, and offset by half the original stroke width to retain its bounds.
KiCad's native polygon fracture preserves the aperture in one filled polygon.
It has no pads or mask/copper objects and the same assembly exclusions.
The original outline asset remains available, unmodified.
Footprints:JLCPCB_QR_Placeholder_5mm is newly authored as a zero-outline-width,
filled 5 × 5mm silk rectangle, following JLC's marking instructions
checked 2026-11-02. It has no pads, copper, mask openings, paste or model.
Both assets are PCB-only and excluded from assembly data. The quote exporter
accepts only their exact reference/footprint pairs and verifies zero pads plus
both exclusion flags. Panel validation checks native artwork transformations.
WROOM routing footprint variants — 2026-10-31¶
Current module: ESP32-S3-WROOM-1-N16R8. The overlapping WROOM-2 ground
extension from the historical placement record below is removed. The active
Footprints:ESP32-S3-WROOM-1_BandOverhang keeps the stock WROOM-1 perimeter pads,
3.9 × 3.9mm underside ground land, nine paste windows, twelve thermal drills
and 3D model reference. Its off-board antenna silkscreen is trimmed.
Two other project-global variants avoid board-specific silk collisions:
Footprints:GT-USB-7010AO_BandOverhang trims off-board socket outline silk;
Footprints:INA232A_RightBand trims the outline beside J202. No numbered pad,
drill, paste or courtyard geometry changes accompany either silk adjustment.
The schematic fields and placed board footprints use the same names. Native
readback verifies their pad geometry against the saved library definitions;
full DRC includes footprint-library parity and has no findings. The U203
JLCPCB_CORRECTION remains 0; 0; 180.
Variants derive from the already selected footprints, not a new ECAD import.
The original library/model provenance and licences remain applicable. Evidence:
build/headband-wroom-routing-20261031/validation.json, layer plots and ERC/DRC.
This is CAD validation; exact WROOM assembly sourcing, rotation and regenerated
panel/manufacturing outputs remain separate gates.
WROOM-1-N16R8 with WROOM-2 ground provision — 2026-10-30¶
Historical placement record, superseded by the WROOM-1-only variant above.
Module: ESP32-S3-WROOM-1-N16R8, replacing the historical MINI below.
Symbol Symbols:ESP32-S3-WROOM-1-N16R8 is in the shared library. It preserves
the existing schematic signal endpoints, using the physical WROOM pad numbers;
three explicit ground pins join the existing ground wire. Footprint
Footprints:ESP32-S3-WROOM-1_2_CommonGND_WROOM1Paste is in shared
../footprints.pretty. No new library nickname or band-local library is added.
Sources: Espressif WROOM-1 datasheet,
v1.8, pin table and recommended PCB land pattern; and
WROOM-2 datasheet,
v1.7, pin table and package/land drawings. The native KiCad 10.0.7 RF_Module
WROOM-1 and WROOM-2 footprints provide the starting geometry; their CC-BY-SA-4.0
licence with library exception remains applicable. Stock source hashes and
saved readback are retained in build/headband-wroom-apply-20261030/library-audit.json.
The stock WROOM-1 3D-model reference is retained; it is not the old MINI model.
Native comparison verifies identical locations/sizes for all 40 perimeter pads between the two stock patterns. The body is 18 × 25.5mm. In unrotated footprint coordinates, X right/Y down:
| Land | Centre, mm | Copper, mm | Paste for fitted WROOM-1 |
|---|---|---|---|
| WROOM-1 ground, pad41 | (−1.50,2.46) | 3.9 × 3.9 | Nine stock 0.9 × 0.9mm windows |
| WROOM-2 ground extension, pad41 | (−1.36,0.09) | 4.0 × 4.0 | None |
The two overlapping ground rectangles are electrically continuous. The new rectangle covers the entire envelope of the stock WROOM-2's nine numbered ground sectors; copying only its first sector would be insufficient. The WROOM-1's twelve 0.2mm thermal drills / 0.6mm copper pads remain. Paste windows are retained from WROOM-1 only. Future WROOM-2 fitting requires a different paste variant and assembly review; the present stencil is not claimed suitable for both.
There are 41 unique numbered electrical pads: ground is 1/40/41, 3V3 is 2, and EN is 3. The active GPIO/pad table records every connected signal. Unconnected physical pads are: 10=GPIO17, 11=GPIO18, 15=GPIO3, 16=GPIO46, 24=GPIO47, 25=GPIO48, 26=GPIO45, 28=GPIO35, 29=GPIO36, 30=GPIO37, 33=GPIO40, 38=GPIO2, 39=GPIO1. Pads 28–30 remain unused for octal PSRAM; pads 24/25 remain unused because WROOM-2 uses a 1.8V I/O domain there. CC interrupt is pad20/GPIO12; BX clocks are pads21/22, GPIO13/14. Neither device addressing nor other components' schematic net assignments changes.
Checks: native footprint/pad readback, exported schematic net comparison, standalone/parent ERC, and board schematic-parity verification. The new symbol and controller sheet were rendered for visual inspection. Exact JLC/LCSC part selection and CPL rotation remain open; the MINI quote supplement is removed. The PCB is a placement checkpoint with unrouted nets, not a manufacturing release.
Espressif ESP32-S3-MINI-1-N8¶
Historical MINI record; the WROOM section above owns the current module.
Source: manufacturer document, v1.7, pp.10–12 and 38–40. Symbol RF_Module:ESP32-S3-MINI-1; footprint RF_Module:ESP32-S2-MINI-1.
View: top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads.
| Physical lead | Function | Symbol pin / name / type | Footprint pad(s), X/Y mm | Evidence |
|---|---|---|---|---|
| 1 | GND | 1 / GND / power_in | 1 (-7, -3.4) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 2 | GND | 2 / GND / passive | 2 (-7, -2.55) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 3 | 3V3 | 3 / 3V3 / power_in | 3 (-7, -1.7) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 4 | IO0 | 4 / IO0 / bidirectional | 4 (-7, -0.85) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 5 | IO1 | 5 / IO1 / bidirectional | 5 (-7, 0) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 6 | IO2 | 6 / IO2 / bidirectional | 6 (-7, 0.85) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 7 | IO3 | 7 / IO3 / bidirectional | 7 (-7, 1.7) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 8 | IO4 | 8 / IO4 / bidirectional | 8 (-7, 2.55) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 9 | IO5 | 9 / IO5 / bidirectional | 9 (-7, 3.4) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 10 | IO6 | 10 / IO6 / bidirectional | 10 (-7, 4.25) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 11 | IO7 | 11 / IO7 / bidirectional | 11 (-7, 5.1) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 12 | IO8 | 12 / IO8 / bidirectional | 12 (-7, 5.95) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 13 | IO9 | 13 / IO9 / bidirectional | 13 (-7, 6.8) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 14 | IO10 | 14 / IO10 / bidirectional | 14 (-7, 7.65) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 15 | IO11 | 15 / IO11 / bidirectional | 15 (-7, 8.5) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 16 | IO12 | 16 / IO12 / bidirectional | 16 (-5.95, 9.55) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 17 | IO13 | 17 / IO13 / bidirectional | 17 (-5.1, 9.55) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 18 | IO14 | 18 / IO14 / bidirectional | 18 (-4.25, 9.55) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 19 | IO15 | 19 / IO15 / bidirectional | 19 (-3.4, 9.55) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 20 | IO16 | 20 / IO16 / bidirectional | 20 (-2.55, 9.55) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 21 | IO17 | 21 / IO17 / bidirectional | 21 (-1.7, 9.55) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 22 | IO18 | 22 / IO18 / bidirectional | 22 (-0.85, 9.55) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 23 | USB_D- | 23 / USB_D- / bidirectional | 23 (0, 9.55) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 24 | USB_D+ | 24 / USB_D+ / bidirectional | 24 (0.85, 9.55) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 25 | IO21 | 25 / IO21 / bidirectional | 25 (1.7, 9.55) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 26 | IO26 | 26 / IO26 / bidirectional | 26 (2.55, 9.55) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 27 | IO47 | 27 / IO47 / bidirectional | 27 (3.4, 9.55) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 28 | IO33 | 28 / IO33 / bidirectional | 28 (4.25, 9.55) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 29 | IO34 | 29 / IO34 / bidirectional | 29 (5.1, 9.55) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 30 | IO48 | 30 / IO48 / bidirectional | 30 (5.95, 9.55) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 31 | IO35 | 31 / IO35 / bidirectional | 31 (7, 8.5) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 32 | IO36 | 32 / IO36 / bidirectional | 32 (7, 7.65) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 33 | IO37 | 33 / IO37 / bidirectional | 33 (7, 6.8) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 34 | IO38 | 34 / IO38 / bidirectional | 34 (7, 5.95) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 35 | IO39 | 35 / IO39 / bidirectional | 35 (7, 5.1) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 36 | IO40 | 36 / IO40 / bidirectional | 36 (7, 4.25) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 37 | IO41 | 37 / IO41 / bidirectional | 37 (7, 3.4) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 38 | IO42 | 38 / IO42 / bidirectional | 38 (7, 2.55) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 39 | TXD0 | 39 / TXD0 / bidirectional | 39 (7, 1.7) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 40 | RXD0 | 40 / RXD0 / bidirectional | 40 (7, 0.85) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 41 | IO45 | 41 / IO45 / bidirectional | 41 (7, 0) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 42 | GND | 42 / GND / passive | 42 (7, -0.85) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 43 | GND | 43 / GND / passive | 43 (7, -1.7) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 44 | IO46 | 44 / IO46 / bidirectional | 44 (7, -2.55) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 45 | EN | 45 / EN / input | 45 (7, -3.4) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 46 | GND | 46 / GND / passive | 46 (5.95, -4.45) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 47 | GND | 47 / GND / passive | 47 (5.1, -4.45) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 48 | GND | 48 / GND / passive | 48 (4.25, -4.45) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 49 | GND | 49 / GND / passive | 49 (3.4, -4.45) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 50 | GND | 50 / GND / passive | 50 (2.55, -4.45) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 51 | GND | 51 / GND / passive | 51 (1.7, -4.45) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 52 | GND | 52 / GND / passive | 52 (0.85, -4.45) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 53 | GND | 53 / GND / passive | 53 (0, -4.45) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 54 | GND | 54 / GND / passive | 54 (-0.85, -4.45) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 55 | GND | 55 / GND / passive | 55 (-1.7, -4.45) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 56 | GND | 56 / GND / passive | 56 (-2.55, -4.45) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 57 | GND | 57 / GND / passive | 57 (-3.4, -4.45) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 58 | GND | 58 / GND / passive | 58 (-4.25, -4.45) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 59 | GND | 59 / GND / passive | 59 (-5.1, -4.45) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 60 | GND | 60 / GND / passive | 60 (-5.95, -4.45) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 61 | GND | 61 / GND / passive | 61 (-1.65, 0.9); 61 (-1.65, 2.55); 61 (-1.65, 4.2); 61 (0, 0.9); 61 (0, 2.55); 61 (0, 4.2); 61 (1.65, 0.9); 61 (1.65, 2.55); 61 (1.65, 4.2) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 62 | GND | 62 / GND / passive | 62 (-7, -4.45) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 63 | GND | 63 / GND / passive | 63 (-7, 9.55) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 64 | GND | 64 / GND / passive | 64 (7, 9.55) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
| 65 | GND | 65 / GND / passive | 65 (7, -4.45) | v1.7, pp.10–12 and 38–40; top/component; 1 at left upper side, anticlockwise; 61 exposed GND split into nine CAD pads |
Reconciliation: 65 symbol electrical pins; 73 electrical copper pad records; 0 unnumbered mechanical holes. The module has 65 named electrical lands; pad61 is partitioned into nine GND copper/paste lands in the standard footprint (eight extra CAD records), all intentionally the same GND connection. The S2-named footprint is the matching 65-pin MINI mechanical pattern selected by the standard S3 symbol. No unresolved mirror or lead-function ambiguity remains for schematic use.
Placement check, 2026-10-25: the stock S2-named footprint's Fab body is
15.4 × 20.0mm; the selected S3 module's manufacturer envelope is
15.4 × 20.5mm, including the 5.05mm antenna area. Retain the audited pad pattern,
but use the actual S3 body and RF reservation drawn on User.Drawings for
mechanical fit. At the first placement the S3 extends 5.05mm beyond the rear
PCB edge, reaching 37.55mm from the front. The annotated review includes this
envelope. A fresh comparison with v1.7 figure 11-1 (PDF p.45) confirms the
0.85mm-pitch, 0.4 × 0.8mm perimeter lands, four 0.8mm corner lands and nine
1.2mm thermal-pad sectors on a 1.65mm grid. The copper is retained. Thermal
vias shown in the manufacturer example remain a routing-stage task.
The placed instance now uses the locally retained
S3 manufacturer STEP, with its own
documented offset; the stock S2 Fab drawing is still only a legacy envelope.
Pre-bridged solder jumpers and mousebite fixture¶
Project-authored features, 2026-10-26; no MPN, distributor ID, paste or fitted
component. Both custom jumper footprints live in the shared
espurr/footprints.pretty library and use the stock Jumper:SolderJumper_2_Bridged
symbol. They replace the first mask-covered net ties for individual cut/re-solder tests.
| Footprint | Pad 1 / pad 2, footprint-local mm | Copper / intent |
|---|---|---|
SolderJumper_2_Bridged_1.4x0.8mm_Neck0.2mm |
(−0.4,0) / (+0.4,0), each 0.6 × 0.8mm | F.Cu; 0.20mm neck; 1.4 × 0.8mm overall copper/mask window |
SolderJumper_2_Bridged_2.3x1.0mm_Neck0.75mm |
(−0.65,0) / (+0.65,0), each 1.0 × 1.0mm | F.Cu; 0.75mm neck; 2.3 × 1.0mm overall copper/mask window |
At 90° on the joined board, pad 1 faces the left main below and pad 2 faces
the right main above. Each has two passive symbol pins and two roundrect copper
pads, with a filled copper neck overlapping each pad by 0.05mm. Pad group 1,2
and the footprint's solder-mask-bridge allowance cover the intentional join.
F.Mask exposes the pads and neck together; there is no F.Paste or mechanical hole.
The courtyard adds 0.1mm around the pad bounds. Schematic and PCB exclusions
prevent BOM/position entries. Original JP references and board centres are retained.
The old NetTie_Breakaway_* library assets are retained as unused checkpoint assets.
BreakawayTabs_16x8mm_NPTH0.5 is a board-only fixture with 20 unnumbered
0.5mm NPTH holes, a 2 × 10mm rounded Edge.Cuts slot and two multilayer rule
areas; it has no symbol or electrical pad/net assignment. The
bridge record
documents all coordinates, intentional hole spacing and remaining acceptance
gates. Native saved readback verifies pad groups, layer sets, exclusions,
holes and rule areas; native DRC verifies the connected outline, internal slot
and unchanged global clearances. Physical separation/current and manufacturer
acceptance remain unverified.
Silergy SY8301ABC — superseded 2026-10-26¶
This is the historical six-pin selection. The current five-pin SY8089A1 block and its retained Olimex land pattern are documented at the end of this audit.
Source: manufacturer document, AN_SY8301 Rev0.9A, pp.2,10. Symbol Symbols:SY8301ABC; footprint Package_TO_SOT_SMD:SOT-23-6.
View: top/component; 1 upper-left, 2 middle-left, 3 lower-left, then anticlockwise.
| Physical lead | Function | Symbol pin / name / type | Footprint pad(s), X/Y mm | Evidence |
|---|---|---|---|---|
| 1 | BS | 1 / BS / passive | 1 (-1.1375, -0.95) | AN_SY8301 Rev0.9A, pp.2,10; top/component; 1 upper-left, 2 middle-left, 3 lower-left, then anticlockwise |
| 6 | LX | 6 / LX / passive | 6 (1.1375, -0.95) | AN_SY8301 Rev0.9A, pp.2,10; top/component; 1 upper-left, 2 middle-left, 3 lower-left, then anticlockwise |
| 5 | IN | 5 / IN / power_in | 5 (1.1375, 0) | AN_SY8301 Rev0.9A, pp.2,10; top/component; 1 upper-left, 2 middle-left, 3 lower-left, then anticlockwise |
| 4 | EN | 4 / EN / input | 4 (1.1375, 0.95) | AN_SY8301 Rev0.9A, pp.2,10; top/component; 1 upper-left, 2 middle-left, 3 lower-left, then anticlockwise |
| 3 | FB | 3 / FB / input | 3 (-1.1375, 0.95) | AN_SY8301 Rev0.9A, pp.2,10; top/component; 1 upper-left, 2 middle-left, 3 lower-left, then anticlockwise |
| 2 | GND | 2 / GND / power_in | 2 (-1.1375, 0) | AN_SY8301 Rev0.9A, pp.2,10; top/component; 1 upper-left, 2 middle-left, 3 lower-left, then anticlockwise |
Reconciliation: 6 symbol electrical pins; 6 electrical copper pad records; 0 unnumbered mechanical holes. No unresolved mirror or lead-function ambiguity remains for schematic use.
Hynetek HUSB320-BA000-QN12R¶
Source: manufacturer document, Rev1.2, pp.4–5,27. Symbol Symbols:HUSB320-BA000-QN12R; footprint Footprints:HUSB320_QFN-12_1.6x1.6mm.
View: top/component; 1 upper-left-side; 3–6 bottom left-to-right; 9–12 top right-to-left.
| Physical lead | Function | Symbol pin / name / type | Footprint pad(s), X/Y mm | Evidence |
|---|---|---|---|---|
| 1 | CC1 | 1 / CC1 / bidirectional | 1 (-0.65, -0.2) | Rev1.2, pp.4–5,27; top/component; 1 upper-left-side; 3–6 bottom left-to-right; 9–12 top right-to-left |
| 2 | CC2 | 2 / CC2 / bidirectional | 2 (-0.65, 0.2) | Rev1.2, pp.4–5,27; top/component; 1 upper-left-side; 3–6 bottom left-to-right; 9–12 top right-to-left |
| 3 | PORT | 3 / PORT / input | 3 (-0.6, 0.725) | Rev1.2, pp.4–5,27; top/component; 1 upper-left-side; 3–6 bottom left-to-right; 9–12 top right-to-left |
| 4 | VBUS_DET | 4 / VBUS_DET / input | 4 (-0.2, 0.725) | Rev1.2, pp.4–5,27; top/component; 1 upper-left-side; 3–6 bottom left-to-right; 9–12 top right-to-left |
| 5 | ADDR | 5 / ADDR / input | 5 (0.2, 0.725) | Rev1.2, pp.4–5,27; top/component; 1 upper-left-side; 3–6 bottom left-to-right; 9–12 top right-to-left |
| 11 | ~{EN} | 11 / ~{EN} / input | 11 (-0.2, -0.725) | Rev1.2, pp.4–5,27; top/component; 1 upper-left-side; 3–6 bottom left-to-right; 9–12 top right-to-left |
| 6 | ~{INT} | 6 / ~{INT} / open_collector | 6 (0.6, 0.725) | Rev1.2, pp.4–5,27; top/component; 1 upper-left-side; 3–6 bottom left-to-right; 9–12 top right-to-left |
| 7 | SDA | 7 / SDA / bidirectional | 7 (0.65, 0.2) | Rev1.2, pp.4–5,27; top/component; 1 upper-left-side; 3–6 bottom left-to-right; 9–12 top right-to-left |
| 8 | SCL | 8 / SCL / input | 8 (0.65, -0.2) | Rev1.2, pp.4–5,27; top/component; 1 upper-left-side; 3–6 bottom left-to-right; 9–12 top right-to-left |
| 9 | ID | 9 / ID / open_collector | 9 (0.6, -0.725) | Rev1.2, pp.4–5,27; top/component; 1 upper-left-side; 3–6 bottom left-to-right; 9–12 top right-to-left |
| 10 | GND | 10 / GND / power_in | 10 (0.2, -0.725) | Rev1.2, pp.4–5,27; top/component; 1 upper-left-side; 3–6 bottom left-to-right; 9–12 top right-to-left |
| 12 | VDD | 12 / VDD / power_in | 12 (-0.6, -0.725) | Rev1.2, pp.4–5,27; top/component; 1 upper-left-side; 3–6 bottom left-to-right; 9–12 top right-to-left |
Reconciliation: 12 symbol electrical pins; 12 electrical copper pad records; 0 unnumbered mechanical holes. Twelve perimeter leads, no exposed centre pad. The four longer side leads use different land lengths from the eight top/bottom leads. Nominal lead dimensions plus toe extension define this land proposal; assembly/stencil acceptance remains open. No unresolved mirror or lead-function ambiguity remains for schematic use.
Clearance refinement, 2026-10-25: the eight short-lead land rows move outward by 0.025mm, from Y ±0.700 to ±0.725mm. Pad dimensions and the four long side-lead lands are unchanged; minimum copper gap becomes 0.150mm. The manufacturer supplies package dimensions, not a recommended PCB land pattern; this remains our land proposal. Nominal terminal overlap remains, with the short-lead inner edge at 0.475mm versus the nominal terminal heel at 0.500mm. Confirm assembly/stencil acceptance; no clearance-rule exception is used.
ST LSM6DSV16BXTR¶
Source: manufacturer document, DS13771 Rev3, pp.9–11,132. Symbol Symbols:LSM6DSV16BXTR; footprint Package_LGA:LGA-14_3x2.5mm_P0.5mm_LayoutBorder3x4y.
View: top/component; datasheet bottom view reflected about Y; 1 upper-left, anticlockwise.
| Physical lead | Function | Symbol pin / name / type | Footprint pad(s), X/Y mm | Evidence |
|---|---|---|---|---|
| 1 | SA0/SDO | 1 / SA0/SDO / bidirectional | 1 (-1.1625, -0.75) | DS13771 Rev3, pp.9–11,132; top/component; datasheet bottom view reflected about Y; 1 upper-left, anticlockwise |
| 2 | TDMOUT | 2 / TDMOUT / output | 2 (-1.1625, -0.25) | DS13771 Rev3, pp.9–11,132; top/component; datasheet bottom view reflected about Y; 1 upper-left, anticlockwise |
| 3 | BCLK | 3 / BCLK / input | 3 (-1.1625, 0.25) | DS13771 Rev3, pp.9–11,132; top/component; datasheet bottom view reflected about Y; 1 upper-left, anticlockwise |
| 4 | INT1 | 4 / INT1 / output | 4 (-1.1625, 0.75) | DS13771 Rev3, pp.9–11,132; top/component; datasheet bottom view reflected about Y; 1 upper-left, anticlockwise |
| 5 | VDD_IO | 5 / VDD_IO / power_in | 5 (-0.5, 0.9125) | DS13771 Rev3, pp.9–11,132; top/component; datasheet bottom view reflected about Y; 1 upper-left, anticlockwise |
| 6 | AH1/QVAR1 | 6 / AH1/QVAR1 / passive | 6 (0, 0.9125) | DS13771 Rev3, pp.9–11,132; top/component; datasheet bottom view reflected about Y; 1 upper-left, anticlockwise |
| 7 | GND | 7 / GND / power_in | 7 (0.5, 0.9125) | DS13771 Rev3, pp.9–11,132; top/component; datasheet bottom view reflected about Y; 1 upper-left, anticlockwise |
| 8 | VDD | 8 / VDD / power_in | 8 (1.1625, 0.75) | DS13771 Rev3, pp.9–11,132; top/component; datasheet bottom view reflected about Y; 1 upper-left, anticlockwise |
| 9 | AH2/QVAR2 | 9 / AH2/QVAR2 / passive | 9 (1.1625, 0.25) | DS13771 Rev3, pp.9–11,132; top/component; datasheet bottom view reflected about Y; 1 upper-left, anticlockwise |
| 10 | INT2 | 10 / INT2 / output | 10 (1.1625, -0.25) | DS13771 Rev3, pp.9–11,132; top/component; datasheet bottom view reflected about Y; 1 upper-left, anticlockwise |
| 11 | WCLK | 11 / WCLK / input | 11 (1.1625, -0.75) | DS13771 Rev3, pp.9–11,132; top/component; datasheet bottom view reflected about Y; 1 upper-left, anticlockwise |
| 12 | ~{CS} | 12 / ~{CS} / input | 12 (0.5, -0.9125) | DS13771 Rev3, pp.9–11,132; top/component; datasheet bottom view reflected about Y; 1 upper-left, anticlockwise |
| 13 | SCL | 13 / SCL / input | 13 (0, -0.9125) | DS13771 Rev3, pp.9–11,132; top/component; datasheet bottom view reflected about Y; 1 upper-left, anticlockwise |
| 14 | SDA | 14 / SDA / bidirectional | 14 (-0.5, -0.9125) | DS13771 Rev3, pp.9–11,132; top/component; datasheet bottom view reflected about Y; 1 upper-left, anticlockwise |
Reconciliation: 14 symbol electrical pins; 14 electrical copper pad records; 0 unnumbered mechanical holes. No unresolved mirror or lead-function ambiguity remains for schematic use.
TI INA701AYWFR¶
Source: manufacturer document, SBOSAM2 Aug2025, pp.3,41–43. Symbol Symbols:INA701AYWFR; footprint Footprints:INA701_YWF0008A.
View: top/component; A1 upper-left, columns1–3 left-to-right; rowsA–C top-to-bottom.
| Physical lead | Function | Symbol pin / name / type | Footprint pad(s), X/Y mm | Evidence |
|---|---|---|---|---|
| A3 | IN+ | A3 / IN+ / passive | A3 (0.387, -0.400) | SBOSAM2 Aug2025, pp.3,41–43; top/component; A1 upper-left, columns1–3 left-to-right; rowsA–C top-to-bottom |
| A1 | IN- | A1 / IN- / passive | A1 (-0.387, -0.400) | SBOSAM2 Aug2025, pp.3,41–43; top/component; A1 upper-left, columns1–3 left-to-right; rowsA–C top-to-bottom |
| B2 | A0 | B2 / A0 / input | B2 (0, 0.102) | SBOSAM2 Aug2025, pp.3,41–43; top/component; A1 upper-left, columns1–3 left-to-right; rowsA–C top-to-bottom |
| B3 | SDA | B3 / SDA / bidirectional | B3 (0.4, 0.102) | SBOSAM2 Aug2025, pp.3,41–43; top/component; A1 upper-left, columns1–3 left-to-right; rowsA–C top-to-bottom |
| C3 | SCL | C3 / SCL / input | C3 (0.4, 0.502) | SBOSAM2 Aug2025, pp.3,41–43; top/component; A1 upper-left, columns1–3 left-to-right; rowsA–C top-to-bottom |
| C2 | ~{ALERT} | C2 / ~{ALERT} / open_collector | C2 (0, 0.502) | SBOSAM2 Aug2025, pp.3,41–43; top/component; A1 upper-left, columns1–3 left-to-right; rowsA–C top-to-bottom |
| C1 | VS | C1 / VS / power_in | C1 (-0.4, 0.502) | SBOSAM2 Aug2025, pp.3,41–43; top/component; A1 upper-left, columns1–3 left-to-right; rowsA–C top-to-bottom |
| B1 | GND | B1 / GND / power_in | B1 (-0.4, 0.102) | SBOSAM2 Aug2025, pp.3,41–43; top/component; A1 upper-left, columns1–3 left-to-right; rowsA–C top-to-bottom |
Reconciliation: 8 symbol electrical pins; 8 electrical copper pad records; 0 unnumbered mechanical holes. There is no A2 ball. A1/A3 are 0.300×0.404mm integrated-shunt power lands; B/C lands are 0.200×0.200mm. Their A-row X pitch is 0.774mm, while B/C pitch is 0.400mm. The 0.102mm row-B displacement relative to body centre is intentional. NSMD/paste process, escape copper and supplier WCSP approval remain layout/release gates. No unresolved mirror or lead-function ambiguity remains for schematic use.
Correction on 2026-10-25: the initial footprint placed row A at Y=-0.298mm by reading the drawing's 0.400mm A-to-package-centreline dimension as A-to-B pitch. Row A belongs at Y=-0.400mm; row B remains at +0.102mm and row C at +0.502mm. A-to-B centre spacing is 0.502mm, giving a 0.200mm copper gap after subtracting the two half-pad heights. The two shunt pads now also use the drawing's typical R0.05 corners, and the A1 marker follows the corrected row. The silk boundary is moved clear of the corrected lands. Native pad readback checks all eight centres, sizes and R0.05 corners; a disposable coupon with the band's project constraints passes DRC with no findings. The reported 0.098mm gap described the erroneous footprint, not TI's land pattern.
Lite-On LTR-F216A¶
Source: manufacturer document, cached BNS-OD-FC002/A4, pp.2,29. Symbol Symbols:LTR-F216A; footprint Footprints:LTR-F216A.
View: top/component; 1 lower-left, 2 bottom-centre, 3 lower-right, 4 upper-right, 5 top-centre, 6 upper-left.
| Physical lead | Function | Symbol pin / name / type | Footprint pad(s), X/Y mm | Evidence |
|---|---|---|---|---|
| 1 | VDD | 1 / VDD / power_in | 1 (-0.65, 0.8) | cached BNS-OD-FC002/A4, pp.2,29; top/component; 1 lower-left, 2 bottom-centre, 3 lower-right, 4 upper-right, 5 top-centre, 6 upper-left |
| 3 | GND | 3 / GND / power_in | 3 (0.65, 0.8) | cached BNS-OD-FC002/A4, pp.2,29; top/component; 1 lower-left, 2 bottom-centre, 3 lower-right, 4 upper-right, 5 top-centre, 6 upper-left |
| 4 | SCL | 4 / SCL / input | 4 (0.65, -0.8) | cached BNS-OD-FC002/A4, pp.2,29; top/component; 1 lower-left, 2 bottom-centre, 3 lower-right, 4 upper-right, 5 top-centre, 6 upper-left |
| 6 | SDA | 6 / SDA / bidirectional | 6 (-0.65, -0.8) | cached BNS-OD-FC002/A4, pp.2,29; top/component; 1 lower-left, 2 bottom-centre, 3 lower-right, 4 upper-right, 5 top-centre, 6 upper-left |
| 5 | ~{INT} | 5 / ~{INT} / open_collector | 5 (0, -0.8) | cached BNS-OD-FC002/A4, pp.2,29; top/component; 1 lower-left, 2 bottom-centre, 3 lower-right, 4 upper-right, 5 top-centre, 6 upper-left |
| 2 | NC | 2 / NC / no_connect | 2 (0, 0.8) | cached BNS-OD-FC002/A4, pp.2,29; top/component; 1 lower-left, 2 bottom-centre, 3 lower-right, 4 upper-right, 5 top-centre, 6 upper-left |
Reconciliation: 6 symbol electrical pins; 6 electrical copper pad records; 0 unnumbered mechanical holes. Six physical leads including NC2. Pad centres are ±0.65mm X, ±0.8mm Y; 0.3×0.5mm lands include toe allowance beyond the nominal 0.4mm component terminals. Optical detector opening and LED-spill shielding are layout gates. No unresolved mirror or lead-function ambiguity remains for schematic use.
Torex XC6206P332MR-G¶
Source: manufacturer document, XC6206 Series, pp.2,12–13. Symbol Regulator_Linear:XC6206PxxxMR; footprint Package_TO_SOT_SMD:SOT-23-3.
View: top/component; 1 upper-left, 2 lower-left, 3 right.
| Physical lead | Function | Symbol pin / name / type | Footprint pad(s), X/Y mm | Evidence |
|---|---|---|---|---|
| 1 | GND | 1 / GND / power_in | 1 (-1.1375, -0.95) | XC6206 Series, pp.2,12–13; top/component; 1 upper-left, 2 lower-left, 3 right |
| 2 | VO | 2 / VO / power_out | 2 (-1.1375, 0.95) | XC6206 Series, pp.2,12–13; top/component; 1 upper-left, 2 lower-left, 3 right |
| 3 | VI | 3 / VI / power_in | 3 (1.1375, 0) | XC6206 Series, pp.2,12–13; top/component; 1 upper-left, 2 lower-left, 3 right |
Reconciliation: 3 symbol electrical pins; 3 electrical copper pad records; 0 unnumbered mechanical holes. No unresolved mirror or lead-function ambiguity remains for schematic use.
Hirose FH34SRJ-10S-0.5SH(50)¶
Source: manufacturer document, FH34SRJ catalog Nov2018, pp.3–4. Symbol Symbols:FH34SRJ-10S-0.5SH; footprint Footprints:HRS_FH34SRJ-10S-0.5SH.
View: top/component PCB view; contact1 right, descending X; matching FPC bottom-contact numbering opposite top-contact numbering.
| Physical lead | Function | Symbol pin / name / type | Footprint pad(s), X/Y mm | Evidence |
|---|---|---|---|---|
| 1 | 1 | 1 / 1 / passive | 1 (2.25, -1.15) | FH34SRJ catalog Nov2018, pp.3–4; top/component PCB view; contact1 right, descending X; matching FPC bottom-contact numbering opposite top-contact numbering |
| 2 | 2 | 2 / 2 / passive | 2 (1.75, -1.15) | FH34SRJ catalog Nov2018, pp.3–4; top/component PCB view; contact1 right, descending X; matching FPC bottom-contact numbering opposite top-contact numbering |
| 3 | 3 | 3 / 3 / passive | 3 (1.25, -1.15) | FH34SRJ catalog Nov2018, pp.3–4; top/component PCB view; contact1 right, descending X; matching FPC bottom-contact numbering opposite top-contact numbering |
| 4 | 4 | 4 / 4 / passive | 4 (0.75, -1.15) | FH34SRJ catalog Nov2018, pp.3–4; top/component PCB view; contact1 right, descending X; matching FPC bottom-contact numbering opposite top-contact numbering |
| 5 | 5 | 5 / 5 / passive | 5 (0.25, -1.15) | FH34SRJ catalog Nov2018, pp.3–4; top/component PCB view; contact1 right, descending X; matching FPC bottom-contact numbering opposite top-contact numbering |
| 6 | 6 | 6 / 6 / passive | 6 (-0.25, -1.15) | FH34SRJ catalog Nov2018, pp.3–4; top/component PCB view; contact1 right, descending X; matching FPC bottom-contact numbering opposite top-contact numbering |
| 7 | 7 | 7 / 7 / passive | 7 (-0.75, -1.15) | FH34SRJ catalog Nov2018, pp.3–4; top/component PCB view; contact1 right, descending X; matching FPC bottom-contact numbering opposite top-contact numbering |
| 8 | 8 | 8 / 8 / passive | 8 (-1.25, -1.15) | FH34SRJ catalog Nov2018, pp.3–4; top/component PCB view; contact1 right, descending X; matching FPC bottom-contact numbering opposite top-contact numbering |
| 9 | 9 | 9 / 9 / passive | 9 (-1.75, -1.15) | FH34SRJ catalog Nov2018, pp.3–4; top/component PCB view; contact1 right, descending X; matching FPC bottom-contact numbering opposite top-contact numbering |
| 10 | 10 | 10 / 10 / passive | 10 (-2.25, -1.15) | FH34SRJ catalog Nov2018, pp.3–4; top/component PCB view; contact1 right, descending X; matching FPC bottom-contact numbering opposite top-contact numbering |
| MP | MP | MP / MP / passive | MP (-3.25, 1.35); MP (3.25, 1.35) | FH34SRJ catalog Nov2018, pp.3–4; top/component PCB view; contact1 right, descending X; matching FPC bottom-contact numbering opposite top-contact numbering |
Reconciliation: 11 symbol electrical pins; 12 electrical copper pad records; 0 unnumbered mechanical holes. Ten physical contacts plus two electrical retention tabs: both tabs use MP, producing 11 symbol pins and 12 footprint pads. Per-contact F.Mask and F.Paste are explicit polygons, not pad layer flags; all ten openings/paste sectors are present. Retained shared STEP model provenance is recorded in the shared project model notes. No unresolved mirror or lead-function ambiguity remains for schematic use.
G-Switch GT-USB-7010AO and GT-USB-7010ASV¶
The 2026-11-02 rear-view check confirmed that all sixteen numbered contact pads
are F.Cu/F.Mask/F.Paste only. The four SH anchors are plated through as intended.
The fitted C963413 STEP asset places its contact seating face at Z=-1.68mm;
GT-USB-7010AO_BandOverhang, the base
USB_C_Receptacle_G-Switch_GT-USB-7010ASV, and J101 now use a +1.68mm model-only
Z offset. The base footprint's unresolved alternative STEP reference is replaced
with the same fitted C963413 asset.
This removes the false rear contact comb without changing pads, masks, copper,
placement or the STEP file. The source model's generic internal filename and
colours remain illustrative; this is a seating correction, not model qualification.
J101 uses GT-USB-7010AO / C963413, orange. The black GT-USB-7010ASV / C2988369 is the alternative. Sources are G-Switch's orange drawing, GT-USB-7010A Rev A0, 2023-02-01, p.1 (explicit orange UL94V-0 housing), and ASV drawing, GT-USB-7010ASV Rev A0, 2023-02-04, p.1. Catalogue identities are C963413 and C2988369, both Extended when checked 2026-10-25. AO is rated 5A; ASV 3A. This does not change the headband's USB current contract.
Retain Connector:USB_C_Receptacle_USB2.0_16P and select the shared derivative
Footprints:USB_C_Receptacle_G-Switch_GT-USB-7010ASV for either colour.
Both drawings show the same component-side PCB pattern: X right, Y down,
contacts along the rear edge, left-to-right A1/B12 through A12/B1. The coordinates
below are the actual library and saved disposable-board readback; each row uses
that component-side view and the p.1 pin/land-pattern evidence above.
| Physical lead | Function | Symbol pin / name / type | Footprint pad, X/Y mm |
|---|---|---|---|
| A1 | GND | A1 / GND / passive | A1 (-3.20, -3.760) |
| B12 | GND | B12 / GND / passive | B12 (-3.20, -3.760) |
| A4 | VBUS | A4 / VBUS / passive | A4 (-2.40, -3.725) |
| B9 | VBUS | B9 / VBUS / passive | B9 (-2.40, -3.725) |
| B8 | SBU2 | B8 / SBU2 / bidirectional | B8 (-1.75, -3.725) |
| A5 | CC1 | A5 / CC1 / bidirectional | A5 (-1.25, -3.725) |
| B7 | D− | B7 / D− / bidirectional | B7 (-0.75, -3.725) |
| A6 | D+ | A6 / D+ / bidirectional | A6 (-0.25, -3.725) |
| A7 | D− | A7 / D− / bidirectional | A7 (+0.25, -3.725) |
| B6 | D+ | B6 / D+ / bidirectional | B6 (+0.75, -3.725) |
| A8 | SBU1 | A8 / SBU1 / bidirectional | A8 (+1.25, -3.725) |
| B5 | CC2 | B5 / CC2 / bidirectional | B5 (+1.75, -3.725) |
| A9 | VBUS | A9 / VBUS / passive | A9 (+2.40, -3.725) |
| B4 | VBUS | B4 / VBUS / passive | B4 (+2.40, -3.725) |
| A12 | GND | A12 / GND / passive | A12 (+3.20, -3.760) |
| B1 | GND | B1 / GND / passive | B1 (+3.20, -3.760) |
| Rear left shell stake | Shield | SH / SHIELD / passive | SH (-4.32, -3.125) |
| Rear right shell stake | Shield | SH / SHIELD / passive | SH (+4.32, -3.125) |
| Front left shell stake | Shield | SH / SHIELD / passive | SH (-4.32, +1.075) |
| Front right shell stake | Shield | SH / SHIELD / passive | SH (+4.32, +1.075) |
| Left locating peg | Mechanical | Absent: non-electrical | unnumbered (-2.89, -2.605), Ø0.65mm NPTH |
| Right locating peg | Mechanical | Absent: non-electrical | unnumbered (+2.89, -2.605), Ø0.65mm NPTH |
Reconciliation: 16 contacts at 12 solder locations, four shell stakes and two locating pegs. The symbol has 17 electrical pins, including one SH pin; the footprint has 20 numbered copper pad records (four coincident A/B pairs plus four SH records), and two unnumbered mechanical holes. The body is 8.94 × 7.35mm, USB centre height 1.68mm. Signal pads are 0.30 × 1.24mm; paired power pads are 0.60 × 1.24mm. Paired GND pads are 0.60 × 1.17mm, centred at Y −3.760mm; all have front copper/mask/paste. Rear SH lands are 1.0 × 2.1mm with 0.6 × 1.7mm plated slots; front SH lands are 1.0 × 1.8mm with 0.6 × 1.4mm slots. The library extends the contact lands beyond the drawing's nominal contact reach. Peg and stake centres, slot widths and electrical ordering agree.
The G-Switch and USB4105 footprints are close but differ: contact-row Y is -3.725 versus -3.68mm, contact land length 1.24 versus 1.15mm, and rear SH centre Y -3.125 versus -3.105mm. The G-Switch standard footprint has no SH paste openings, whereas the GCT footprint includes SH paste. Confirm the shell-stake solder process/paste and retention with JLC before release; JLC currently flags the AO's assembly difficulty as High. Check peg/stake fit, protrusion and solder access on the final rigid stack; the ASV drawing recommends 0.80mm PCB thickness; the selected headband order target is now nominal 1.6mm JLC04161H-7628, with the physical dimensions recorded in the rigid setup. The standard 3D model represents the ASV and does not prove an orange visual or the final mounted assembly.
Acceptance evidence is under build/headband-sourcing-2026-10-25/: both rendered
manufacturer drawings, connector-trial/saved-readback.json, numbered Fab/copper
plot and usb-power.png. Konnect placed the disposable footprint; KiCad 10
pcbnew independently read its saved pads and kicad-cli plotted it. J101's
symbol UUID, placement and connections are retained. The per-lead mapping is
accepted for schematic/footprint assignment; fabrication and PCBA checks remain
open. The initial assignment used the standard footprint directly. The later
clearance refinement below promotes a bounded derivative to the shared library.
Clearance refinement, 2026-10-25: KiCad 10.0.7's stock merged GND pads have 0.1944mm clearance to the Ø0.65mm locating holes. This is below both the project's 0.25mm floor and JLC's published 0.20mm NPTH-to-track floor. The derivative retains the holes and every other land, but moves GND pad centres 0.035mm away from the pegs and shortens those lands by 0.070mm. The opposite copper edge stays fixed. The resulting 0.2626mm minimum gap passes native DRC without a scoped or global rule relaxation. There are four changed CAD records because each physical GND land has two coincident pin numbers. Copper, mask and paste follow the shortened lands. See KiCad derivative attribution.
GCT USB4105-GF-A (superseded selection)¶
Retained as the initial schematic's audit record. J101 now uses the G-Switch selection above; this section is not its current footprint assignment.
Source: manufacturer document, USB4105 drawing B4 18Dec2023, p.1. Symbol Connector:USB_C_Receptacle_USB2.0_16P; footprint Connector_USB:USB_C_Receptacle_GCT_USB4105-xx-A_16P_TopMnt_Horizontal.
View: component-side PCB land pattern; left-to-right A1/B12,A4/B9,B8,A5,B7,A6,A7,B6,A8,B5,A9/B4,A12/B1.
| Physical lead | Function | Symbol pin / name / type | Footprint pad(s), X/Y mm | Evidence |
|---|---|---|---|---|
| A1 | GND | A1 / GND / passive | A1 (-3.2, -3.68) | USB4105 drawing B4 18Dec2023, p.1; component-side PCB land pattern; left-to-right A1/B12,A4/B9,B8,A5,B7,A6,A7,B6,A8,B5,A9/B4,A12/B1 |
| A4 | VBUS | A4 / VBUS / passive | A4 (-2.4, -3.68) | USB4105 drawing B4 18Dec2023, p.1; component-side PCB land pattern; left-to-right A1/B12,A4/B9,B8,A5,B7,A6,A7,B6,A8,B5,A9/B4,A12/B1 |
| A5 | CC1 | A5 / CC1 / bidirectional | A5 (-1.25, -3.68) | USB4105 drawing B4 18Dec2023, p.1; component-side PCB land pattern; left-to-right A1/B12,A4/B9,B8,A5,B7,A6,A7,B6,A8,B5,A9/B4,A12/B1 |
| A6 | D+ | A6 / D+ / bidirectional | A6 (-0.25, -3.68) | USB4105 drawing B4 18Dec2023, p.1; component-side PCB land pattern; left-to-right A1/B12,A4/B9,B8,A5,B7,A6,A7,B6,A8,B5,A9/B4,A12/B1 |
| A7 | D- | A7 / D- / bidirectional | A7 (0.25, -3.68) | USB4105 drawing B4 18Dec2023, p.1; component-side PCB land pattern; left-to-right A1/B12,A4/B9,B8,A5,B7,A6,A7,B6,A8,B5,A9/B4,A12/B1 |
| A8 | SBU1 | A8 / SBU1 / bidirectional | A8 (1.25, -3.68) | USB4105 drawing B4 18Dec2023, p.1; component-side PCB land pattern; left-to-right A1/B12,A4/B9,B8,A5,B7,A6,A7,B6,A8,B5,A9/B4,A12/B1 |
| A9 | VBUS | A9 / VBUS / passive | A9 (2.4, -3.68) | USB4105 drawing B4 18Dec2023, p.1; component-side PCB land pattern; left-to-right A1/B12,A4/B9,B8,A5,B7,A6,A7,B6,A8,B5,A9/B4,A12/B1 |
| A12 | GND | A12 / GND / passive | A12 (3.2, -3.68) | USB4105 drawing B4 18Dec2023, p.1; component-side PCB land pattern; left-to-right A1/B12,A4/B9,B8,A5,B7,A6,A7,B6,A8,B5,A9/B4,A12/B1 |
| B1 | GND | B1 / GND / passive | B1 (3.2, -3.68) | USB4105 drawing B4 18Dec2023, p.1; component-side PCB land pattern; left-to-right A1/B12,A4/B9,B8,A5,B7,A6,A7,B6,A8,B5,A9/B4,A12/B1 |
| B4 | VBUS | B4 / VBUS / passive | B4 (2.4, -3.68) | USB4105 drawing B4 18Dec2023, p.1; component-side PCB land pattern; left-to-right A1/B12,A4/B9,B8,A5,B7,A6,A7,B6,A8,B5,A9/B4,A12/B1 |
| B5 | CC2 | B5 / CC2 / bidirectional | B5 (1.75, -3.68) | USB4105 drawing B4 18Dec2023, p.1; component-side PCB land pattern; left-to-right A1/B12,A4/B9,B8,A5,B7,A6,A7,B6,A8,B5,A9/B4,A12/B1 |
| B6 | D+ | B6 / D+ / bidirectional | B6 (0.75, -3.68) | USB4105 drawing B4 18Dec2023, p.1; component-side PCB land pattern; left-to-right A1/B12,A4/B9,B8,A5,B7,A6,A7,B6,A8,B5,A9/B4,A12/B1 |
| B7 | D- | B7 / D- / bidirectional | B7 (-0.75, -3.68) | USB4105 drawing B4 18Dec2023, p.1; component-side PCB land pattern; left-to-right A1/B12,A4/B9,B8,A5,B7,A6,A7,B6,A8,B5,A9/B4,A12/B1 |
| B8 | SBU2 | B8 / SBU2 / bidirectional | B8 (-1.75, -3.68) | USB4105 drawing B4 18Dec2023, p.1; component-side PCB land pattern; left-to-right A1/B12,A4/B9,B8,A5,B7,A6,A7,B6,A8,B5,A9/B4,A12/B1 |
| B9 | VBUS | B9 / VBUS / passive | B9 (-2.4, -3.68) | USB4105 drawing B4 18Dec2023, p.1; component-side PCB land pattern; left-to-right A1/B12,A4/B9,B8,A5,B7,A6,A7,B6,A8,B5,A9/B4,A12/B1 |
| B12 | GND | B12 / GND / passive | B12 (-3.2, -3.68) | USB4105 drawing B4 18Dec2023, p.1; component-side PCB land pattern; left-to-right A1/B12,A4/B9,B8,A5,B7,A6,A7,B6,A8,B5,A9/B4,A12/B1 |
| SH | SHIELD | SH / SHIELD / passive | SH (-4.32, -3.105); SH (-4.32, 1.075); SH (4.32, -3.105); SH (4.32, 1.075) | USB4105 drawing B4 18Dec2023, p.1; component-side PCB land pattern; left-to-right A1/B12,A4/B9,B8,A5,B7,A6,A7,B6,A8,B5,A9/B4,A12/B1 |
| Mechanical hole | Board locating peg | Absent: non-electrical | unnumbered (-2.89, -2.605), drill 0.65×0.65mm | USB4105 drawing B4 18Dec2023, p.1; component-side PCB land pattern; left-to-right A1/B12,A4/B9,B8,A5,B7,A6,A7,B6,A8,B5,A9/B4,A12/B1 |
| Mechanical hole | Board locating peg | Absent: non-electrical | unnumbered (2.89, -2.605), drill 0.65×0.65mm | USB4105 drawing B4 18Dec2023, p.1; component-side PCB land pattern; left-to-right A1/B12,A4/B9,B8,A5,B7,A6,A7,B6,A8,B5,A9/B4,A12/B1 |
Reconciliation: 17 symbol electrical pins; 20 electrical copper pad records; 2 unnumbered mechanical holes. The 16 contacts use twelve unique solder positions: paired GND/VBUS contacts have coincident A/B-numbered pad records; four shell-stake pads share SH, and two unnumbered NPTHs locate the housing. These duplicate copper geometries are intentional. The mating-face view is separately checked in the drawing; the PCB layout explicitly says component side. No unresolved mirror or lead-function ambiguity remains for schematic use.
ST USBLC6-2SC6¶
Source: manufacturer document, DS4260 Rev7 Dec2021, pp.1,12. Symbol Power_Protection:USBLC6-2SC6; footprint Package_TO_SOT_SMD:SOT-23-6.
View: top/component; 1 upper-left, 2 middle-left, 3 lower-left, then anticlockwise.
| Physical lead | Function | Symbol pin / name / type | Footprint pad(s), X/Y mm | Evidence |
|---|---|---|---|---|
| 1 | I/O1 | 1 / I/O1 / passive | 1 (-1.1375, -0.95) | DS4260 Rev7 Dec2021, pp.1,12; top/component; 1 upper-left, 2 middle-left, 3 lower-left, then anticlockwise |
| 2 | GND | 2 / GND / passive | 2 (-1.1375, 0) | DS4260 Rev7 Dec2021, pp.1,12; top/component; 1 upper-left, 2 middle-left, 3 lower-left, then anticlockwise |
| 3 | I/O2 | 3 / I/O2 / passive | 3 (-1.1375, 0.95) | DS4260 Rev7 Dec2021, pp.1,12; top/component; 1 upper-left, 2 middle-left, 3 lower-left, then anticlockwise |
| 4 | I/O2 | 4 / I/O2 / passive | 4 (1.1375, 0.95) | DS4260 Rev7 Dec2021, pp.1,12; top/component; 1 upper-left, 2 middle-left, 3 lower-left, then anticlockwise |
| 5 | VBUS | 5 / VBUS / passive | 5 (1.1375, 0) | DS4260 Rev7 Dec2021, pp.1,12; top/component; 1 upper-left, 2 middle-left, 3 lower-left, then anticlockwise |
| 6 | I/O1 | 6 / I/O1 / passive | 6 (1.1375, -0.95) | DS4260 Rev7 Dec2021, pp.1,12; top/component; 1 upper-left, 2 middle-left, 3 lower-left, then anticlockwise |
Reconciliation: 6 symbol electrical pins; 6 electrical copper pad records; 0 unnumbered mechanical holes. No unresolved mirror or lead-function ambiguity remains for schematic use.
Non-IC provisions¶
Generic unpolarised R/C/L, fuses, push switches, test pads and two-pad solder jumpers use standard KiCad symbols with pin1/pin2 checked before wiring. A generic passive symbol does not freeze procurement. Supporting passive and tactile-switch MPNs still need the normal BOM/land check before routing/ordering. No footprints have been transferred to the source band PCB.
Bourns SRP4020TA-4R7M / C2041623¶
Source: manufacturer data sheet, page 1, top/component land view. Symbol Device:L; footprint Footprints:Bourns_SRP4020TA. Selected 4.7uH ±20%, 3.5A saturation, 2.6A RMS, maximum 105mΩ DCR.
| Physical terminal | Symbol pin / type | Footprint pad, X/Y mm | Land size mm |
|---|---|---|---|
| Left winding end | 1 / passive | 1 (-1.85, 0) | 1.5 × 2.4 |
| Right winding end | 2 / passive | 2 (1.85, 0) | 1.5 × 2.4 |
Two electrical terminals and two copper pads; no additional contacts or mechanical holes. Unpolarised. The recommended pattern is 5.2mm overall with a 2.2mm inner gap. Body nominal 4.45 × 4.06mm with maximum 4.70 × 4.31mm accounted for by the courtyard. Pads, Fab body and courtyard were queried back after creation.
Littelfuse 0467002.NR / C122964 — retired from the band¶
F101 was removed on 2026-10-25; USB VBUS now feeds 5V_L directly. This
retained footprint record documents the unused shared-library asset, not a
current BOM requirement.
Source: manufacturer 467-series data sheet, revision 11/09/17, pages 1–3, cached as datasheets/Littelfuse-467.pdf. Symbol Device:Fuse; footprint Footprints:Littelfuse_467_0603. The original selection was a 2A very fast thin-film fuse, 0603 (1608); availability was unresolved. The original choice avoided a high-resistance PTC because the buck input minimum is 4.5V.
| Physical terminal | Symbol pin / type | Footprint pad, X/Y mm | Land size mm |
|---|---|---|---|
| First end cap | 1 / passive | 1 (-0.889, 0) | 0.762 × 1.09 |
| Second end cap | 2 / passive | 2 (0.889, 0) | 0.762 × 1.09 |
Two electrical terminals and two copper pads; no mechanical holes. Unpolarised. This is the manufacturer's reflow pattern: 2.54mm overall, 1.02mm inner gap, 1.09mm pad width. It deliberately differs from the generic KiCad 0603 fuse land.
Manual power feed and joined-test copper¶
J105/J205 use Connector_Generic:Conn_01x02 and Footprints:WirePower_28AWG_2Pads_P3.0mm: terminal/pin/pad 1 is the local 5V rail and terminal/pin/pad 2 is the local ground. Pads are 1.5 × 3.0mm at X=-1.5/+1.5mm, Y=0, front copper/mask, no paste. Two electrical pads, no holes or extra contacts. This is a hand-solder provision for the separate 28AWG silicone wire pair; mechanical strain support remains a PCB/enclosure task.
JP101–JP106, JP108 and JP109 are eight sacrificial joined-test copper paths (six signals, 5V and GND), represented by Jumper:SolderJumper_2_Bridged. They are not purchased components. The compact exposed-copper footprints above permit independent cut/re-solder tests. Their centres, mousebite geometry and plane/via pull-back are placed; traces remain unrouted. Power-current capacity and physical separation still need qualification. Remove power before cutting or separating, verify isolation, then fit the FFC/power pair and retest. The two 3.3V regulators are never connected in parallel.
First schematic contract and remaining gates¶
Both INA701 ALERT outputs and both ALS INT outputs are explicitly unused; firmware polls the devices. INA701 A0 straps select 0x54 (GND) and 0x55 (VS), confirmed against table 6-2. BX SA0 uses a 10k pulldown, preserving the bidirectional SDO function's symbol type without an ERC exclusion. The later manual revision removes all four external LED DIN pulldowns; retain 100Ω source resistors and the intended blank-frame startup policy. PDM DATA has no pulls.
The selected remote mic is Gettop MD-DRA371-H10 / C50275760, with the existing breakout acceptance record as its physical-map evidence. It is documented at the main microphone sockets; a microphone flex PCB is a separate design task. Nominal 3.3V operation, including regulator tolerance above the recommended 3.3V maximum, is an explicit user-accepted assumption. The right logic regulator is XC6206P332MR-G / C5446 with 2.2uF input/output ceramics, upstream of the measured ear feed.
Cable contact identity, both reversible mic insertion orientations, microphone opening/support, 28AWG strain relief, effective capacitor values, input inrush/drop, mounted BX coupling and the actual 2.048MHz clock jitter/receiver alignment remain physical or layout gates. The BX clock requirement includes maximum 4ns p-p jitter and ±0.1% frequency tolerance; nominal S3 divider calculations do not establish those measurements. Supporting passive sourcing and supplier paste/assembly acceptance remain open.
XUNPU TS-1088-AR02016 / C720477¶
SW101 RESET, SW102 APP1 and SW103 APP2 use Switch:SW_Push and
Footprints:SW_SPST_TS-1088-xR020. The latter is an unchanged copy of the
KiCad 10.0.7 stock footprint, including its installed-library 3D-model reference;
no EasyEDA conversion was needed. See the licence notice.
The pinned source SHA256 is
4e1702eb881097d7c7b80a35c685950a3ce7d1b2d8d7169f5a096bacf3ba7a8b;
the disposable import/provenance record is under
build/library-trials/ts-1088-2026-10-25/provenance.json.
Source: manufacturer TS-1088-ARXXXX drawing, Rev A, sheet 1, top/component and recommended PCB land views. AR has no locating pegs; 020 selects 2.0mm height, 16 selects 160gf nominal force. Body is 3.90 × 3.00mm, metal terminal span 5.00mm and actuator diameter 1.80mm.
| Physical terminal, top view | Symbol pin / type | Footprint pad, X/Y mm | Land size mm |
|---|---|---|---|
| Left terminal 1 | 1 / passive | 1 (-2.225, 0) | 1.05 × 2.00 |
| Right terminal 2 | 2 / passive | 2 (2.225, 0) | 1.05 × 2.00 |
Two terminals, two normally open symbol pins and two front SMD roundrect pads;
no extra contacts, mechanical pads or holes. Pads include F.Cu/F.Paste/F.Mask.
Their outside span is 5.50mm and inner gap 3.40mm, matching the drawing. Fab
shows the body and actuator; the 6.00 × 3.50mm courtyard extends 0.25mm beyond
the copper/body envelope. Silk is clipped clear of the lands. Saved native pad
readback and a rendered disposable coupon confirm the geometry; coupon DRC is
clean. These checks do not establish assembly yield or mounted switch durability.
JLC's official component API returned componentLibraryType: base on 2026-10-25;
the symbols carry MPN, manufacturer, LCSC ID, datasheet and sourcing fields.
The schematic source was authored through Konnect in an isolated copy because nested standalone/parent project ownership blocked placement in place. Native KiCad UI supplied missing text repositioning and title-block operations. The five saved sheets are promoted byte-identically, preserving root/child UUIDs and hierarchy. Formal netlist/ERC/PDF outputs remain under build/headband-schematic-2026-10-25/; the source PCB, project names, worksheets and original library aliases remain intact.
Saved-file validation on 2026-10-25 with KiCad 10.0.7 found 0 errors / 0 warnings for the standalone band, 96 netlisted components and 82 nets. All 346 intended pin/net assignments and all 20 sheet-level wiring/component/short/orphan checks passed. Independent CLI exports confirmed the MCU/FFC maps, local monitor/LDO branches, eight test paths and unchanged band connectivity in the parent hierarchy. The parent snapshot has two unrelated unconnected ear sensing pins (U1 CS1/CS3); its band sheets have no findings. These checks do not qualify physical cable mappings, PCB current paths or mounted operation.
Wired redraw and module-pad review — 2026-10-25¶
The five sheets now draw local circuits with wires and standard power:VDD /
power:GND symbols whose Values name the separate rails. Saved readback confirms
441 orthogonal wire segments, 78 named power symbols and no ordinary rail labels.
The current GPIO map
moves seven MCU connections after reviewing physical module pads against the
mounting concept; actual PCB placement/routing remains open.
All 96 physical components retain their selected parts, footprints and fields. Their UUIDs are preserved except J104, recreated with the supported mirror option to face its matching socket in the overview. Its contact map is unchanged; root/child sheet UUIDs and project settings are preserved.
Independent CLI exports from disposable copies confirm all 346 connected pin assignments after those seven GPIO moves, with 25 intentional NC pins. There are now 86 raw nets: each USBLC6 uses separate external input/output nets for its internally common 1/6 and 3/4 channels. Joining those four device-internal pairs gives the same 82 electrical partitions as the first draft, including NC pins. All nine named power rails and all parent-context band connections are preserved, with no accidental band/ear net joins.
Standalone ERC remains 0 errors / 0 warnings; the fresh parent snapshot has
only the same two unrelated ear U1 CS1/CS3 findings. The five-page PDF was visually
reviewed, including field/annotation spacing. Evidence and source-preservation
hashes are under build/headband-schematic-redraw-2026-10-25/, with independent
exports under root-review/promoted/. PCB, cable, assembly and mounted-operation
gates above remain open.
Input, controls and rigid stack update — 2026-10-25¶
F101 is removed and its two rails are one 5V_L net, including the USB socket,
protection-device rail pins and HUSB320 VBUS detector. The redundant second
power flag and its stub are removed. The three switches use the audited XUNPU
part above, with source component UUIDs and all switch wiring preserved.
The rigid stack is standard JLC04161H-7628; the USB class is 0.219mm width /
0.127mm gap using the calculator result recorded in the
rigid profile.
Independent KiCad 10.0.7 exports confirm 92 components / 85 nets, with only
the former USB_VBUS/5V_L partition merge and F101 removal. Standalone and
parent ERC both have 0 errors / 0 warnings, and all band pin partitions
match in the parent hierarchy. Saved native readback checks effective classes,
and native IPC-2581 export confirms the 7628 materials/dielectric thicknesses.
Both disposable switch and corrected INA701 coupons pass DRC. The source band
PCB is still empty; its missing-outline DRC finding is expected and is not a
layout acceptance result. Evidence remains under
build/headband-controls-2026-10-25/. Mounted behaviour and supplier assembly
eligibility remain separate checks.
SY8089A1 and compact BOOT jumper — 2026-10-26¶
The manual power revision selects SY8089A1AAC / C479074. Its existing shared
symbol is named Symbols:SY8089AAAC; the instance's Value/MPN identifies A1.
The Silergy A1 datasheet
confirms 1 EN, 2 GND, 3 LX, 4 IN, 5 FB, 0.6V feedback, 2.5–5.5V input and
1.5MHz switching. The pin functions match the saved symbol and exported nets.
Andi retained OLIMEX_Regulators-FP:SOT-23-5 from the locally installed
Olimex KiCad library, following the
ESP32-S3-DevKit-LiPo Rev B.
That reference uses SY8089AAAC rather than A1. No new library import or licence
grant is implied. Native readback of the existing land pattern gives:
| Pad / function | Unrotated local centre (mm) | Copper land (mm) |
|---|---|---|
| 1 EN | −1.30, −0.95 | 1.20 × 0.55 |
| 2 GND | −1.30, 0 | 1.20 × 0.55 |
| 3 LX | −1.30, 0.95 | 1.20 × 0.55 |
| 4 IN | 1.30, 0.95 | 1.20 × 0.55 |
| 5 FB | 1.30, −0.95 | 1.20 × 0.55 |
The original selected footprint has no Fab body/courtyard; placement review therefore also uses the package envelope. The first routing keeps the inductor body clear of the regulator's lead ends. Native DRC is a copper check and does not establish the missing courtyard or physical assembly clearance.
New shared Footprints:SolderJumper_2_Open_P1.3mm_Pad1.0x0.9mm is an original,
two-pad service footprint for JP1 BOOT. Both rounded pads are 1.00 × 0.90mm,
centred at x=±0.65mm, with a 0.30mm gap and 2.30 × 0.90mm copper envelope.
Layers are F.Cu/F.Mask with no paste; no component, 3D model or assembly entry.
The 180° placed instance retains BOOT on pad 1 and GND_L on pad 2, and is
excluded from BOM and position exports. Konnect authored the library footprint;
independent native and live readback check the actual pad dimensions and nets.
The eight existing shared bridged-jumper footprints are restored without
changing their pad/net identities. They retain their intentional 1,2 net-tie
groups and solder-mask bridge flags. Konnect's library refresh rejects those
groups, so supported native KiCad refreshed them on a guarded copy, followed by
live readback, independent netlist/ERC and DRC checks. The current checkpoint
has no footprint/library mismatch or schematic-parity finding.
FFC mask ownership and revised breakaway fixture — 2026-10-26¶
HRS_FH34SRJ-10S-0.5SH now generates the ten contact mask openings from the
numbered pads: F.Cu/F.Mask, +0.05mm mask margin, with the imported
standalone mask polygons removed. Each aperture retains its 0.4 × 0.9mm
bounding box; the expanded pad rounds its corners by 0.05mm. Native before/after
mask plots verify this limited difference, with mounting-pad apertures retained.
The separate paste graphics, copper dimensions, pin numbering, body, model and
provenance are unchanged.
The contact pads have 0.15mm local clearance to keep unrelated pours outside
the openings and the project's unchanged 0.09mm mask-to-copper floor. All six
band instances are refreshed. The ear master instance is intentionally untouched.
An earlier review trial omitted F.Mask from the contact layer sets and closed
the openings; its zero mask-error count must not be treated as validation.
BreakawayTabs_16x8mm_NPTH0.5 retains its 16 × 8mm nominal web and two fracture
rows but moves the rounded slot centre to local x=8.975mm, with slot edges
7.975/9.975mm. Each row has six holes at local x=0.6/1.8/3.0/4.2/5.4/6.6mm
and three at 11.1/13.1/15.1mm, for 18 NPTH holes total. Slot Y limits and
all-layer no-pour/no-via/non-front-track restrictions are retained. This puts
six signal jumpers on the left offcut and the two power jumpers on the right,
with the slot clear of both fixed connector courtyards. Physical separation
and supplier acceptance remain open.
U103's schematic now agrees with the manually selected PCB footprint
Package_TO_SOT_SMD:SOT-23-5; the older Olimex land-pattern table above is
historical. Value/MPN, pin functions and the 100kΩ/22kΩ/22pF circuit are retained.
INA232A and external shunts — 2026-10-27¶
This applied selection supersedes the INA701 section for U106/U203. The old
symbol/footprint remain available for historical designs; they are not fitted
on the current band PCB. New assets remain in the shared Symbols: and
Footprints: libraries.
TI INA232AIDDFR / C5447660 uses Symbols:INA232AIDDFR and
Footprints:INA232_DDF0008A. Evidence: TI SBOSAA2, December 2022,
p.3 pin table/top view and appended DDF0008A drawing 4222047/E (July 2024),
land-pattern page 36 of the downloaded PDF. Top/component view, X right/Y down,
1 at upper left, counterclockwise numbering. Eight physical leads, eight symbol
pins, eight electrical pads; no duplicates, exposed pad or mechanical pads.
| Lead/function | Symbol pin / type | Footprint pad | X / Y, mm |
|---|---|---|---|
| 1 IN+ | 1 / input | 1 | −1.30 / −0.975 |
| 2 IN− | 2 / input | 2 | −1.30 / −0.325 |
| 3 GND | 3 / power_in | 3 | −1.30 / +0.325 |
| 4 VS | 4 / power_in | 4 | −1.30 / +0.975 |
| 5 SCL | 5 / input | 5 | +1.30 / +0.975 |
| 6 SDA | 6 / bidirectional | 6 | +1.30 / +0.325 |
| 7 A0 | 7 / input | 7 | +1.30 / −0.325 |
| 8 ALERT | 8 / open_collector | 8 | +1.30 / −0.975 |
All eight lands are 1.05 × 0.45mm, 0.65mm pitch, R0.05 rounded corners, with 0.20mm copper gaps. F.Cu/F.Mask/F.Paste are present. The body outline is 1.65 × 2.9mm, courtyard 4.2 × 3.6mm, with upper-left pin-1 silk/fab indicators. The imported EasyEDA part was inspected as a reference, but its pad geometry and body-sized courtyard were not promoted. The new footprint was authored from TI's drawing through Konnect, then placed and read back with native KiCad.
Milliohm HoYH0603-1/2W-10mR-1%-TCR50 / C2912774 uses Device:R and
Footprints:HoYH0603_10mR, fitted as R132/R202. Evidence:
manufacturer HoYH Ho-A0 specification,
body p.2 and recommended lands p.5, R006–R075 row. This is an unpolarised,
two-terminal part; lead numbering is the design's consistent upstream/load
assignment, not a manufacturer polarity mark.
| Terminal/function | Symbol pin / type | Footprint pad | X / Y, mm |
|---|---|---|---|
| Upstream 5V | 1 / passive | 1 | −0.95 / 0 |
| Downstream EAR_5V | 2 / passive | 2 | +0.95 / 0 |
Two physical terminals, two symbol pins and two rectangular copper/paste/mask
lands. Each land is 1.30 × 0.92mm, with 0.60mm inner gap, matching the
manufacturer's D/W/P dimensions. Nominal body 1.70 × 0.90mm; courtyard
3.70 × 1.60mm also covers the maximum body width. The provided
C2912774_R0603 import had smaller 0.806 × 0.864mm lands and a courtyard inside
its pad envelope. It was not promoted; the corrected asset is newly authored
from the manufacturer drawing, with no imported third-party ECAD geometry.
Kelvin traces leave the inner land edges separately from the load-current paths.
Both assets were queried back, placed in a disposable PCB and visually checked
against the drawings. The symbol was also placed/rendered before source use.
Evidence is under build/headband-ina232-20261027/, including
footprint-trial.png, datasheet-page images, source schematic crops,
final-verification.json and final source DRC. No new 3D models are supplied.
Manufacturer documents retain their rights; these project-authored ECAD assets
follow the repository's licensing. Physical/supplier acceptance remains separate.