MD-DRA371-H10 PDM microphone breakout¶
Independent KiCad 10 project: 14 x 16 mm T-shape, two-layer rigid FR4, 1.6 mm,
1 oz copper, green mask, ENIG. Front-side SMT assembly: U1, C1, R1. Fit J1
manually after reflow. Open md-dra371-h10.kicad_pro in KiCad 10.
The header crossbar is 14 x 6.5 mm; the microphone stem is 8 mm wide.
External and internal corners have 0.6 mm radii. PCB area is approximately
167 mm², about 44% less than the original 15 x 20 mm rectangle.
Connections¶
J1 is a standard 1x5, 2.54 mm header. Pin 1 has the square pad and dot; the front labels identify every pin. With the header above the microphone, viewed from the component side, pins run left to right:
| Pin | Signal | ESP32-S3 example |
|---|---|---|
| 1 | VDD | 3V3 |
| 2 | GND | GND |
| 3 | CLK | GPIO4, PDM clock output |
| 4 | DATA | GPIO5, PDM data input |
| 5 | SEL | Leave open for DATA1; connect to 3V3 for DATA2 |
Use 1.6-3.3 V, with logic levels matching VDD; no pin is 5 V tolerant. At 3.3 V, SEL may be driven directly by another 3.3 V GPIO. R1 is a 100 kohm pulldown, so the default channel works without a fifth jumper. Disable MCU pulls on DATA. Check the selected dev board's pin availability before wiring.
JP1 is the rounded three-pad solder jumper on the front, labelled L / R. It has no paste apertures and is supplied with both bridges open:
| JP1 bridge | Selection | External SEL |
|---|---|---|
| Both open | L / DATA1 through R1's 100k pulldown | GPIO or jumper control allowed |
| Centre to L (pads 1-2) | L / DATA1, SEL hard-strapped to GND | Leave disconnected |
| Centre to R (pads 2-3) | R / DATA2, SEL hard-strapped to VDD | Leave disconnected |
Bridge only one side: bridging all three pads shorts VDD to GND. Remove the solder bridge before driving SEL externally. The centre is SEL, left is GND, right is VDD when viewed from the component side with the header at top. L/R labels denote DATA1/DATA2 here; select the matching receiver channel.
Normal-mode clock range is 1.2-3.3 MHz; 2.4 MHz is the datasheet test point. Allow 20 ms startup. SEL low selects DATA1 (driven after the falling clock edge); SEL high selects DATA2 (driven after the rising edge). Configure the ESP32-S3 PDM receiver's matching channel. For two microphones sharing CLK/DATA, strap one SEL low and the other high. Keep jumper wires short; if the clock rings, fit the datasheet's 50-100 ohm series damping resistor at the ESP32.
Assembly and acoustic path¶
- U1: Gettop MD-DRA371-H10, C50275760 (Extended; listed for Economic/Standard).
- C1: Samsung CL05B104KO5NNNC, C1525, 100 nF, 16 V, X7R, 0402.
- R1: UNI-ROYAL 0402WGF1003TCE, C25741, 100 kohm, 1%, 0402.
- C1525/C25741 are the selected common Basic passive choices; confirm current
category and stock in the assembly order. J1 is excluded from placement and
from the exported assembly BOM/CPL by its
Assembly=Manualproperty. - JP1 is PCB copper, not a purchased component.
Assembly=Copperexcludes it from the assembly BOM/CPL; its pads have no stencil openings.
The microphone listens through the rear of the PCB. Its 0.8 mm NPTH is inside U1, at footprint-local (0, +0.68 mm), and has a 2.0/1.2 mm annular GND sealing land with three separate stencil sectors. Keep the opening clear of adhesive, flux, fixtures, breadboards and enclosure walls. Let the mic end overhang the breadboard or use jumper wires. Do not wash the populated board or blow compressed air into the port. No vias sit between C1 and either mic supply connection.
Manufacturing and checks¶
From the repository root, run just mic-breakout. All generated Gerbers,
separate PTH/NPTH drills, BOM, CPL, source hashes and ERC/DRC reports go under
build/breakouts/md-dra371-h10/release/; source files are never written by the
export recipe. Upload only its fabrication ZIP plus BOM.csv and CPL.csv.
The recorded five-board order used single-sided top Economic PCBA, green / 1.6 mm / ENIG / two layers / 1 oz. The 2026-10-16 capability review permitted this board size, 0402 passives and ENIG with this stackup, without assembly rails or fiducials. Recheck order-time constraints for a repeat. Use the supplied F.Paste rather than the rejected catalogue footprint's paste. Stencil target: 0.10 mm; confirm JLC's microphone process preserves the 0.14 mm webs and keeps paste/cleaning fluid out of the port.
At the 2026-10-16 checkpoint, KiCad 10.0.7 ERC/DRC, including schematic parity, passed with zero findings. See LIBRARY.md for the accepted physical pin map and import audit. The separate Konnect aggregate audit completed all six checks. Its generic power heuristics flag no on-board 10uF bulk capacitor and no dedicated power test point: this minimal breakout uses the dev board's regulated/decoupled 3V3 source, and J1's VDD/GND pins provide probe access. The required local 100nF is fitted. JLC's final placement/DFM preview and actual acoustic/electrical testing remain order/bench checks: verify U1's upper-left pin-1 marker, front side, rotation and open rear port against the supplier-final files when available. Andi reported placing the five-board order; the dated record preserves original upload inputs and distinguishes the later portal placement adjustment from supplier-final files.
Sources checked 2026-10-16: Gettop datasheet, pp. 7-8 and 13, JLC microphone listing, rigid fabrication capabilities, Economic assembly capabilities, C1525, C25741.