LSM6DSV16BX hand-assembly breakout¶
Independent KiCad 10 project for testing hand assembly of ST LSM6DSV16BXTR,
then motion, interrupts and TDM contact audio. Open lsm6dsv16bx.kicad_pro.
The schematic and routed PCB are complete. The board is 28 × 25.4 mm, with
1 mm corner radii, two copper layers and all components on the top. The intended
bare-board build is 1.6 mm FR4, 1 oz copper, green mask, white silk and ENIG.
Use 0402 passives and top-side components only. Andi has hot air and a hotplate. Supply regulated 3.3 V to both VDD and VDD_IO, with 3.3 V logic. There is no regulator, level shifter, power LED or 5 V protection. This project does not change the ears, headband or firmware.
Connections¶
View from the component side, with the part name at the top: J1 is on the left and J2 on the right. Pin 1 is the square top pad on each header; numbers increase downwards. Both headers are ordinary 2.54 mm through-hole parts, with 15.24 mm between rows, installed from the component side. Direct wires are also suitable. The rear carries routing/ground only, with no components. Fit headers after reflowing the SMT parts so they do not obstruct hotplate or hot-air work.
| J1 pin | Signal | Use |
|---|---|---|
| 1 | 3V3 | Regulated input; both IC supplies |
| 2 | GND | Host ground |
| 3 | SDA | I²C SDA / SPI SDI |
| 4 | SCL | I²C SCL / SPI clock |
| 5 | CS_N | Default high through R1; drive for SPI |
| 6 | SA0_SDO | Default low through R2; address select / SPI SDO |
| 7 | INT1 | Programmable interrupt output |
| 8 | INT2 | Programmable interrupt output |
| J2 pin | Signal | Use |
|---|---|---|
| 1 | GND | Audio/analog return |
| 2 | TDMOUT | Audio accelerometer TDM data output in mode 2 |
| 3 | BCLK | TDM bit-clock input |
| 4 | WCLK | TDM word-clock input |
| 5 | QVAR1 | AH1/QVAR1; grounded through fitted R7 |
| 6 | QVAR2 | AH2/QVAR2; grounded through fitted R8 |
Default: I²C at 7-bit address 0x6A. Driving SA0_SDO high selects 0x6B; R2 is a 10 kΩ pulldown, not a hard strap. JP1 is a normally closed copper jumper supplying both 4.7 kΩ I²C pull-ups. Open it for SPI/I3C experiments or when host pull-ups are already sufficient; check isolation after cutting. I3C remains accessible but is not qualified by this design.
R5/R6 weakly bias TDMOUT/BCLK low while unused; they can remain for TDM tests. WCLK has a default internal pull-up and may be left externally unconnected in mode 1. Pin 11 is WCLK, not NC: the mode-1 drawing does not describe its mode-2 function. Keep host outputs quiet until the board is powered.
Remove R7/R8 before using the corresponding Qvar/analog input. With these 0 Ω parts fitted, the header pins are grounded. This is an unprotected bench interface; external electrode protection and worn-use qualification are separate.
Population¶
All purchased parts are for manual assembly. JP1 is PCB copper, without paste. All passives are 0402 / 1005 metric; suitable bench-stock equivalents are fine.
| References | Value | Manufacturer / MPN | LCSC |
|---|---|---|---|
| U1 | LGA-14 IMU, 2.5 × 3 mm, 0.5 mm pitch | STMicroelectronics LSM6DSV16BXTR | C5267394 |
| C1, C2 | 100 nF, 16 V, X7R, ±10% | Samsung CL05B104KO5NNNC | C1525 |
| C3 | 1 µF, 25 V, X5R, ±10% | Samsung CL05A105KA5NQNC | C52923 |
| R1, R2 | 10 kΩ, 1% | UNI-ROYAL 0402WGF1002TCE | C25744 |
| R3, R4 | 4.7 kΩ, 1% | UNI-ROYAL 0402WGF4701TCE | C25900 |
| R5, R6 | 100 kΩ, 1% | UNI-ROYAL 0402WGF1003TCE | C25741 |
| R7, R8 | 0 Ω, removable analog-ground straps | UNI-ROYAL 0402WGF0000TCE | C17168 |
| J1, J2 | 1×8 and 1×6, 2.54 mm | Manual header or direct wires | Unspecified |
Identities, packages and nominal ratings checked 2026-10-30; these are sourcing references, not stock reservations. No purchase or fabrication package is frozen.
Layout and fabrication¶
The PCB uses 0.20 mm normal traces, with short 0.15 mm sensor escapes and a 0.15 mm clearance floor. Vias are 0.60/0.30 mm, tented on both faces; the 14 header holes are 1.0 mm. Filled ground zones cover both faces with thermal connections. C1/C2 have direct supply connections and nearby ground returns. Seven rule areas protect the sensor body/centre/corners from inappropriate tracks, vias and top-side ground fill. The final routes were checked geometrically as well as with DRC; the back ground plane remains beneath the sensor.
For supply sizing, a conservative 10 mA board-load allowance through 50 mm of 0.15 mm × 35 µm copper gives about 0.164 Ω, 1.64 mV drop and 16.4 µW dissipation at 20°C copper resistivity. Actual local supply runs are shorter. This is a low-current sensor breakout, not a power distribution board or controlled- impedance interconnect; keep external clock wires short.
The top labels use at least 1.0 mm text height and 0.15 mm strokes, with 0.15 mm silk clearance to pads. Board copper is at least 0.30 mm from the routed edge. The wider margins put the header labels outside their bodies. The white dot above-left of U1 marks pin 1; do not confuse the neighbouring tented via with that marker.
Use a 0.10 mm top-side stencil. U1's apertures are reduced to approximately
80% of pad area: the native per-side ratio is (sqrt(0.8)-1)/2, producing
approximately 0.559 × 0.313 mm aperture bounds on the 0.625 × 0.350 mm lands
(and the rotated equivalent). Other SMT pads retain their standard paste.
There are 36 paste apertures, none on JP1 or the headers. Do not enlarge
copper for iron-access toes or try to form side fillets on the LGA.
U1 retains the headband's copper geometry, with 25 µm mask expansion and nominal 0.10 mm mask dams. Choose green mask/ENIG and request retained mask bridges at U1. JLC's current capability table advertises 0.10 mm bridges and 1:1 mask openings following a June 2025 LDI upgrade, but its ordering guide still gives a 0.20 mm pad-spacing rule for two-layer boards. Our copper gap is 0.50 − 0.35 = 0.15 mm; subtracting two 0.025 mm expansions leaves the 0.10 mm dam. This fits the capability table, but not the ordering guide's conservative rule. Supplier acceptance remains open until the processed production Gerbers preserve the dams. No order has been placed.
JLCPCB order settings — checked 2026-10-31¶
Use the existing fabrication ZIP. These are recommended selections, not a submitted order or a supplier quote.
| Board option | Selection |
|---|---|
| Material / layers / size | FR4 / 2 / 28 × 25.4 mm |
| Different designs / delivery | 1 / Single PCB |
| Quantity | 5 suggested for soldering trials |
| Thickness / outer copper | 1.6 mm / 1 oz |
| Mask / silkscreen | Green / white |
| Finish | ENIG; standard gold thickness |
| Via covering | Tented; no plugging or filling |
| Outline tolerance | Regular ±0.2 mm |
| Electrical test | Full flying-probe test |
| Confirm Production File | Yes |
| Remove order number | Yes, to preserve the small board's labels |
| Assembly / gold fingers / castellations / edge plating | No |
Put this in PCB Remark, not merely in a text attachment inside the ZIP:
Solder mask bridges are required between U1 pads. U1 has 0.50 mm pitch, 0.35 mm pad width, 0.15 mm copper gap and 0.025 mm mask expansion per side, giving 0.10 mm mask dams. Preserve the supplied U1 mask openings and dams; do not enlarge the openings or merge them into gang openings. If this cannot be manufactured on 2-layer, 1 oz, green-mask ENIG, contact me before production.
Select Review Before Payment if offered, then obtain the engineer's
acceptance. Separately, Confirm Production File provides the processed
Gerbers after payment, before manufacture. Download the production files and
inspect ok/ts (top mask) against ok/tl (top copper) at U1; the rendered
thumbnail alone is insufficient. Keep the 14 pad openings separate, with
nominal 0.10 mm dams and no mask encroachment on their copper lands.
| Stencil option | Selection |
|---|---|
| Order mode | Order together with PCB |
| Type / framework | Solder Paste Stencil / Non-Framework |
| Side / quantity | Top Only / 1 |
| Thickness | Select by Customer: 0.10 mm |
| Custom size | Yes: 100 × 100 mm, single board pattern centred |
| Polishing | Electropolishing |
| Fiducials / nano-coating / step stencil | No / No / No |
The 100 mm square is a practical hand-printing recommendation, with room for a tape hinge and supporting spare boards. Choose a base model whose valid area contains it if the form asks for both a model and a custom cut size. JLC lists 0.10 mm as a standard thickness and recommends electropolishing for ≤0.5 mm pitch. A frame is unnecessary for this manual setup.
Put this in Stencil Remark:
Use lsm6dsv16bx-F_Paste.gtp exactly as supplied, 1:1. No automatic aperture resizing, reduction, enlargement or added openings. U1 paste apertures are already reduced to approximately 80% of pad area. Top only, 0.10 mm thick; centre one board pattern on a 100 × 100 mm frameless stencil. There are 36 apertures. J1, J2 and copper jumper JP1 intentionally have no paste openings. Follow the paste layer only where it differs from solder mask.
JLC normally optimises IC stencil apertures, so this remark avoids a second reduction. The U1 apertures are approximately 0.559 × 0.313 mm; the rectangular area ratio at 0.10 mm thickness is about 1.00. Preserve the existing paste geometry and request stencil production-file confirmation before cutting.
Sources: PCB capabilities, ordering instructions, production-file confirmation, stencil capabilities, frameless/custom stencil ordering.
Bare-board and stencil exports are in
build/breakouts/lsm6dsv16bx/layout-2026-10-31/:
fabrication.zip: two copper layers, both masks, top/bottom silk, top paste, outline, Gerber job file and Excellon drills. Bottom silk and NPTH files contain no objects; there are no underside markings or non-plated holes.hand-assembly-bom.csv: component values, MPNs, LCSC references and assembly notes. JP1 is explicitly marked Copper, not a purchased part.cam-top.png/cam-bottom.png: views rendered from the actual exported CAM.render-delivery/: native raytraced views; generic KiCad component models are illustrative, not mechanical qualification of a particular header or IC lot.
This is a bare-board/hand-assembly package; no PCBA placement file is required.
For a later export, copy the project and shared symbol library into a fresh
build/ tree with their relative paths intact, run ERC/DRC with schematic parity,
and export these exact layers plus separate plated/non-plated drills. Verify
all drill/paste coordinates and source hashes again; do not reuse stale files.
Library provenance¶
The shared Symbols:LSM6DSV16BXTR symbol is unchanged. Its
accepted physical pin map
covers all 14 leads: component-side pin 1 upper-left, numbered anticlockwise,
with no exposed centre pad. The matched copper pattern remains a KiCad library
land proposal, not a manufacturer-supplied footprint.
The project-local BX_Breakout.pretty contains four _HandAssembly derivatives
of KiCad 10.0.7 footprints:
| Upstream footprint | Local changes |
|---|---|
Resistor_SMD:R_0402_1005Metric |
Omit cramped stock silk; board has readable reference text |
Capacitor_SMD:C_0402_1005Metric |
Same silk treatment |
Package_LGA:LGA-14_3x2.5mm_P0.5mm_LayoutBorder3x4y |
Same copper; reduced paste, 25 µm mask expansion, no direct zone connection; board-level body outline/pin-1 dot |
Jumper:SolderJumper-2_P1.3mm_Bridged_RoundedPad1.0x1.5mm |
Same copper bridge/no paste; clearer board-level outline; BOM/position flags match the schematic |
Pad numbers, copper geometry, courtyards and model associations are preserved.
The library is registered through ${KIPRJMOD}/BX_Breakout.pretty; no shared or
installed library was edited. These derivatives retain the KiCad contributors'
CC BY-SA 4.0 licence and design-use exception.
Standard models remain references to the installed KiCad library, not vendored
source assets.
Bring-up and checks¶
Inspect U1 orientation and 3V3–GND resistance, then use current-limited 3.3 V. With CS_N high and SA0 low, start I²C at 100 kHz and read WHO_AM_I register 0x0F: expected 0x71. Enable acceleration/gyro outputs, check stationary readings and orientation changes, then exercise both interrupts. Test TDM separately with a host driving BCLK/WCLK. A working ID transaction does not prove all 14 joints.
The 2026-10-31 completed layout passes KiCad 10.0.7 ERC and DRC with zero errors, warnings, unconnected items or schematic-parity findings. All 14 nets / 52 physical pin endpoints match the intended circuit. The final CAM has 24 plated holes (14 header holes plus 10 vias) and 36 top paste apertures; every hole coordinate/diameter and paste centre/bounding size matches native readback within export precision. Front/rear CAM and the populated render were inspected.
Evidence is in build/breakouts/lsm6dsv16bx/layout-2026-10-31/; the earlier
pre-layout/ directory records the schematic checkpoint. Final source hashes
bind the delivery manifest. Other hardware/shared libraries and frozen orders
are preserved. Firmware was not edited, built or tested. Successful hand
soldering, sensor self-test, audio capture and mounted operation remain bench
checks.
References checked 2026-10-30/31: ST DS13771 datasheet, ST TN0018 Rev 8 soldering guidance, ST register driver, U1 sourcing identity. The cached distributor-hosted ST datasheet is Rev 3, matching the headband audit (pp. 9–11, 132); ST's current web extraction reports Rev 4. The cache is not represented as the latest revision. Download provenance, hashes, rendered pinout/package pages and sourcing responses are retained with the evidence.
Fabrication rules checked 2026-10-31: JLC rigid PCB capabilities and ordering instructions. Quantity, supplier CAM approval and purchase are not set by these exports.