AW93x05 electrode test breakout¶
Independent KiCad 10 project for AW93105DNR, with the same PCB accepting
AW93205DNR or AW93305DNR. These are assembly alternatives, one IC at a time;
their firmware and configuration are different. Open aw93x05.kicad_pro.
The board is 24 × 24 mm, two-layer FR4, 1.6 mm, 1 oz copper, with 1 mm corner radii. Use green solder mask and ENIG for the fine-pitch DFN. SMT parts are on the front. Fit ordinary 2.54 mm headers manually, or solder wires directly to the plated holes. No regulator or power LED is fitted.
Connections¶
View from the component side, with AW93x05 at the top. Pin 1 is square on each
header; pins increase downwards. Supply regulated 3.3 V and use 3.3 V I/O.
This supply works for all three ICs; the board has no 5 V protection or level shifting.
| J1, left edge | Signal | Connection |
|---|---|---|
| 1 | GND | Host ground |
| 2 | 3V3 | Regulated host supply |
| 3 | SDA | I²C data |
| 4 | SCL | I²C clock |
| 5 | INT | Active-low, open-drain INTN; host GPIO |
| J2, right edge | Signal | Suggested initial ear test |
|---|---|---|
| 1 | CS4 | Spare/reference/shield experiment |
| 2 | CS3 | Spare/reference/shield experiment |
| 3 | CS0 | T1: short-side electrode, /TOUCH_SIDE_A |
| 4 | CS1 | T2: long-side electrode, /TOUCH_SIDE_B |
| 5 | CS2 | T3: tip electrode, /TOUCH_TOP |
| 6 | GND | Optional cable/reference ground; do not ground an electrode |
The channel order follows the IC's physical escape routing. Use the printed channel names. The three ear electrodes are independent manual wire connections, not signals on the ear's LED FFC. Start with short, separate leads; avoid bundling them with LED power/data wires.
Population and variants¶
| References | Default | Manufacturer / MPN | LCSC |
|---|---|---|---|
| U1 | AW93105DNR | awinic AW93105DNR | C5241002 |
| R1–R5 | 1 kΩ, 1%, 0603 | UNI-ROYAL 0603WAF1001T5E | C21190 |
| R6–R8 | 4.7 kΩ, 1%, 0603 | UNI-ROYAL 0603WAF4701T5E | C23162 |
| C1 | 1 µF, 50 V, X5R, 0603 | Samsung CL10A105KB8NNNC | C15849 |
| C2 | 100 nF, 50 V, X7R, 0603 | YAGEO CC0603KRX7R9BB104 | C14663 |
| J1, J2 | 1×5 and 1×6, 2.54 mm | Manual header or direct wires | Not in SMT BOM/CPL |
| JP1 | Normally closed copper bridge | PCB copper; no paste | Not in SMT BOM/CPL |
Part identities/specifications were checked on 2026-10-25; availability, Basic/ Extended category, price and any substitution need order-time confirmation. The LCSC page for C15849 did not establish immediate stock. A suitable 1 µF, 0603, X5R/X7R capacitor rated at least 6.3 V may be substituted after confirming its effective capacitance at 3.3 V and assembly footprint.
JP1 supplies both SDA/SCL pull-ups. It is connected by copper as fabricated: cut its narrow exposed bridge to disconnect, and solder across it to reconnect. INTN has a separate, always fitted R8 pull-up. All pull-ups use the IC's own 3.3 V rail, including on AW93305, whose power-sequencing requirement forbids I/O supply preceding VCC. Check continuity after cutting JP1.
R1–R5 are series parts, one per CS channel, close to the IC. The common hardware guide specifies 1 kΩ, overriding the older AW93105 example's 390 Ω. Replace a channel's resistor with 0 Ω only when configuring that channel as driven shield. An ordinary sensing channel retains 1 kΩ. The board does not select shield mode in hardware or tie any CS channels together.
All three variants use default 7-bit I²C address 0x12. CS2 is left free for sensing. AW93105/AW93305 support the documented CS2 address straps, but a strap uses that channel and must be present at reset; this board provides no default address straps. Do not assume that strapping scheme applies to AW93205.
For an AW93205DNR/AW93305DNR assembly, change U1's Value, MPN, LCSC and Datasheet fields to the actual quoted part before regenerating a variant BOM. The default export is AW93105DNR only. Andi is requesting an actual AW93205 quote at 50; the reported MOQ441 / approximately $9 total estimate is not a confirmed quote, stock allocation or purchase. No order or quote request was submitted here.
Bring-up¶
- Check VCC–GND for shorts and inspect the upper-left U1 pin-1 marker. Apply current-limited 3.3 V with host GPIOs unpowered/high impedance until VCC is up.
- Check the local rail and scan for 0x12. Start I²C at 100 kHz. Read the chip ID using the driver/register map for the fitted variant.
- Initialise that variant using its own vendor sequence/configuration. AW93105 runs from ROM; AW93305's supplied MCU example uploads a roughly 15 kB firmware image before configuration. Pin compatibility does not make these interchangeable at the software interface.
- Establish raw/baseline/difference and proximity status with no electrode lead, then each electrode individually. Disable unused channels. Measure noise and drift before tuning thresholds, with LEDs off and then under realistic load.
- Compare bare electrode, fabric and intended fur spacing. Record false triggers, temperature/body effects and recovery after a sustained nearby hand. Only then try a spare reference channel or driven shield.
This is an unprotected bench breakout: no external TVS is fitted or reserved. The guide recommends low-capacitance TVS at an exposed sensor connector; omitting it avoids adding an uncharacterised shunt during the initial sensitivity test. Use ESD handling precautions and do not hot-plug charged electrode leads. A worn or externally handled version needs a verified low-capacitance protection circuit and testing. No through-fur range or mounted behaviour has been demonstrated. Firmware integration is separate; the firmware workspace was not changed.
Layout, export and acceptance¶
CS routes are 0.10 mm, on the front with no signal vias; digital routes stay on the host/IC side. Both ground zones use 0.40 mm clearance. Local ground vias and stitching connect the pours. Supply enters C1, then C2, then U1; C2 is the nearest decoupler. The manufacturer land pattern is retained, including its 0.20 mm pad width and 0.40 mm pitch. See LIBRARY.md for the full pin map.
The 2026-10-25 review passed KiCad 10.0.7 ERC and DRC, including zero unconnected
items and zero schematic-parity findings. Final exports and source fingerprints
are under build/breakouts/aw93x05/release/: fabrication.zip, BOM.csv,
CPL.csv, source copy, netlist, check reports and previews. These are generated
outputs, not committed order records. Gerber/drill and placement coordinates use
the common auxiliary origin at the board's lower-left corner (100, 124 mm in CAD).
Only the 11 SMT designators are in the assembly files; headers and JP1 are omitted.
No dedicated AW93x05 just build recipe has been added. For a refresh, copy the
saved independent project to a new empty build/ directory, run KiCad CLI ERC,
DRC with --schematic-parity, and export Gerbers/drills/positions there. Use
--use-drill-file-origin for Gerbers/positions and --drill-origin plot for
drills; filter the BOM using Assembly=SMT and verify its designators equal CPL.
Compare source hashes before/after, including failure paths. Do not export over
or modify the source project with a generator.
JLC's current pages permit 0.10/0.10 mm tracks for 1 oz, 0.4 mm IC pitch and 24 mm boards on Economic PCBA. Supplier DFM/placement acceptance is still open: the generic fabrication table lists 0.25 × 0.25 mm minimum SMD pads, wider than the manufacturer's 0.20 mm DFN lands. Confirm this exact land pattern, stencil, rotation and sourced IC in the quote/preview. Small 0.8 mm silk legends also fall below JLC's general 1.0 mm text-height guidance; legibility is provisional. If a variant requires Standard PCBA, its larger panel, tooling rails and fiducials must be arranged separately. Clean CAD checks do not close these supplier or bench gates.
Sources checked 2026-10-25: AW93105 datasheet V1.3, AW93205 product and documents, AW933xx datasheet V1.8, the local common hardware guide V1.3 listed in LIBRARY.md, JLC rigid capabilities, JLC assembly capabilities, C5241002, C21190, C23162, C15849, C14663.